diff options
| author | Huang Shijie <b32955@freescale.com> | 2014-01-26 10:58:14 +0800 |
|---|---|---|
| committer | Huang Shijie <b32955@freescale.com> | 2014-01-26 12:18:03 +0800 |
| commit | cc005a1ebc7aa2b963860359bf6ad0d239b5913d (patch) | |
| tree | bd0831f704d8f11df59e237503edb0d665f69e0c | |
| parent | 6952d9fbfed8e58b57e99ef155fbc5b644d7742a (diff) | |
ENGR00296547-2 ARM: dts: imx6qdl-sabreauto: add a new pinctrl for ECSPI1
The ECSPI1 needs the GPIO3_19 to select/de-select the SPI NOR chip.
This patch adds a new pinctrl for this GPIO, and select this pinctrl
when we enable the ECSPI1.
Signed-off-by: Huang Shijie <b32955@freescale.com>
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 461e18a0b7bb..9e9e8b78d32b 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -273,7 +273,7 @@ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 8ccdeb10a581..ea8ec2a501d0 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1072,6 +1072,12 @@ }; ecspi1 { + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + pinctrl_ecspi1_1: ecspi1grp-1 { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |