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authorLaxman Dewangan <ldewangan@nvidia.com>2011-09-27 15:20:07 +0530
committerSimone Willett <swillett@nvidia.com>2011-10-13 12:21:03 -0700
commita9277e51d087437f9246fc4824993bf86cda5533 (patch)
tree7349c636f3b33fb7599fa240243f4dde1ca8fc21
parenta7d3089a4c2dbf51222c9586b0e708b05efe806b (diff)
arm: tegra: cardhu: Support Fab A05
Support for E1291-A05 board. bug 881745 Change-Id: I8307e7cd244cf4b18b06c0ed757bb5a580217ee0 Reviewed-on: http://git-master/r/54665 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-cardhu-power.c19
-rw-r--r--arch/arm/mach-tegra/board-cardhu.h1
2 files changed, 13 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c
index c653e5079713..b43525b554da 100644
--- a/arch/arm/mach-tegra/board-cardhu-power.c
+++ b/arch/arm/mach-tegra/board-cardhu-power.c
@@ -422,8 +422,10 @@ int __init cardhu_regulator_init(void)
}
}
- /* E1291-A04: Enable DEV_SLP and enable sleep on GPIO2 */
- if ((board_info.board_id == BOARD_E1291) && (board_info.fab == BOARD_FAB_A04)) {
+ /* E1291-A04/A05: Enable DEV_SLP and enable sleep on GPIO2 */
+ if ((board_info.board_id == BOARD_E1291) &&
+ ((board_info.fab == BOARD_FAB_A04) ||
+ (board_info.fab == BOARD_FAB_A05))) {
tps_platform.dev_slp_en = true;
tps_platform.gpio_init_data = tps_gpio_pdata_e1291_a04;
tps_platform.num_gpioinit_data =
@@ -704,7 +706,7 @@ GREG_INIT(11, en_vdd_sdmmc1, en_vdd_sdmmc1, "vdd_3v3_devices", 0, 0, T
GREG_INIT(12, en_3v3_pex_hvdd, en_3v3_pex_hvdd, "hvdd_pex_pmu", 0, 0, TEGRA_GPIO_PL7, false, 0, 0, 0, 0);
GREG_INIT(13, en_1v8_cam, en_1v8_cam, "vdd_gen1v8", 0, 0, TEGRA_GPIO_PBB4, false, 0, 0, 0, 0);
-/* E1291-A04 specific */
+/* E1291-A04/A05 specific */
GREG_INIT(1, en_5v0_a04, en_5v0, NULL, 0, 0, TPS6591X_GPIO_8, false, 0, 0, 0, 0);
GREG_INIT(2, en_ddr_a04, en_ddr, NULL, 0, 0, TPS6591X_GPIO_7, false, 0, 0, 0, 0);
GREG_INIT(3, en_3v3_sys_a04, en_3v3_sys, NULL, 0, 0, TPS6591X_GPIO_6, false, 0, 0, 0, 0);
@@ -928,7 +930,7 @@ static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e1291_a03[] = {
E1198_GPIO_REG
};
-/* Gpio switch regulator platform data for E1291 A04*/
+/* Gpio switch regulator platform data for E1291 A04/A05*/
static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e1291_a04[] = {
COMMON_GPIO_REG_E1291_A04
E1291_A03_GPIO_REG
@@ -978,7 +980,8 @@ int __init cardhu_gpio_switch_regulator_init(void)
gswitch_pdata.num_subdevs =
ARRAY_SIZE(gswitch_subdevs_e1291_a03);
gswitch_pdata.subdevs = gswitch_subdevs_e1291_a03;
- } else if (board_info.fab == BOARD_FAB_A04) {
+ } else if ((board_info.fab == BOARD_FAB_A04) ||
+ (board_info.fab == BOARD_FAB_A05)) {
gswitch_pdata.num_subdevs =
ARRAY_SIZE(gswitch_subdevs_e1291_a04);
gswitch_pdata.subdevs = gswitch_subdevs_e1291_a04;
@@ -1063,8 +1066,10 @@ int __init cardhu_suspend_init(void)
tegra_get_board_info(&board_info);
tegra_get_pmu_board_info(&pmu_board_info);
- /* For PMU Fab A03 and A04 make core_pwr_req to high */
- if ((pmu_board_info.fab == BOARD_FAB_A03) || (pmu_board_info.fab == BOARD_FAB_A04))
+ /* For PMU Fab A03, A04 and A05 make core_pwr_req to high */
+ if ((pmu_board_info.fab == BOARD_FAB_A03) ||
+ (pmu_board_info.fab == BOARD_FAB_A04) ||
+ (pmu_board_info.fab == BOARD_FAB_A05))
cardhu_suspend_data.corereq_high = true;
/* CORE_PWR_REQ to be high for all processor/pmu board whose sku bit 0
diff --git a/arch/arm/mach-tegra/board-cardhu.h b/arch/arm/mach-tegra/board-cardhu.h
index 13c32e3a58b2..68bec04e9d70 100644
--- a/arch/arm/mach-tegra/board-cardhu.h
+++ b/arch/arm/mach-tegra/board-cardhu.h
@@ -65,6 +65,7 @@
#define BOARD_FAB_A02 0x2
#define BOARD_FAB_A03 0x3
#define BOARD_FAB_A04 0x4
+#define BOARD_FAB_A05 0x5
/* Display Board ID */
#define BOARD_DISPLAY_PM313 0x030D