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authorPavan Kunapuli <pkunapuli@nvidia.com>2011-02-02 23:20:22 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2011-04-26 15:51:06 -0700
commit4fe14e46a47e07a180533375e2dbea908b3d524b (patch)
tree8d9c010148fa4ee63cbfc9074b1746f8e2e00ba1
parentcbd4b67807be00e26ac4700ec423cb274587fd36 (diff)
arm tegra:Using pll_p clk source for sdmmc instances.
Using pll_p clk source for all sdmmc instances. Disabling clocks left over by the bootloader. Original-Change-Id: I245347b016618c39a4ceb2323f659b09261eaf7d Reviewed-on: http://git-master/r/17847 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I0790f6f67c944a9ca42be9d6b9398d8093b4beef
-rw-r--r--arch/arm/mach-tegra/board-cardhu.c2
-rw-r--r--arch/arm/mach-tegra/clock.c4
-rw-r--r--arch/arm/mach-tegra/common.c7
-rw-r--r--drivers/mmc/host/sdhci-tegra.c12
4 files changed, 4 insertions, 21 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c
index 92ba2c6f80a7..d36b4435206e 100644
--- a/arch/arm/mach-tegra/board-cardhu.c
+++ b/arch/arm/mach-tegra/board-cardhu.c
@@ -153,8 +153,6 @@ static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
{ "i2s2", "pll_a_out0", 11289600, true},
{ "audio", "pll_a_out0", 11289600, true},
{ "audio_2x", "audio", 22579200, true},
- { "sdmmc3", "clk_m", 12000000, true},
- { "sdmmc1", "clk_m", 12000000, true},
{ NULL, NULL, 0, 0},
};
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 73c1f0e87868..3cb0c43925db 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -35,11 +35,7 @@
#include "clock.h"
#include "dvfs.h"
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
#define DISABLE_BOOT_CLOCKS 1
-#else
-#define DISABLE_BOOT_CLOCKS 0 /* !!!FIXME!!! DISABLED FOR EMMC ON CARDHU */
-#endif
/*
* Locking:
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 2b60a0a36bd8..f08d4899ebcb 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -93,10 +93,9 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
/* set frequencies of some device clocks */
{ "pll_u", NULL, 480000000, false },
- { "sdmmc1", "clk_m", 12000000, true},
- { "sdmmc2", "pll_p", 48000000, false},
- { "sdmmc3", "pll_p", 48000000, false},
- { "sdmmc4", "clk_m", 12000000, true},
+ { "sdmmc1", "pll_p", 48000000, true},
+ { "sdmmc3", "pll_p", 48000000, true},
+ { "sdmmc4", "pll_p", 48000000, true},
{ NULL, NULL, 0, 0},
};
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index ad610e82eab3..d17ad5f8bfff 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -106,7 +106,7 @@ static void tegra_sdhci_configure_capabilities(struct sdhci_host *sdhci)
* the vendor clock control register.
*/
ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
- ctrl &= ~(SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE);
+ ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
ctrl &= ~(SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE);
ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING_OVERRIDE;
sdhci_writel(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
@@ -167,10 +167,6 @@ static int __devinit tegra_sdhci_probe(struct platform_device *pdev)
struct resource *res;
int irq;
void __iomem *ioaddr;
- void __iomem *ioaddr_clk_rst;
- void __iomem *ioaddr_pinmux;
- unsigned int val = 0;
-
static struct regulator *reg_sd_slot = NULL;
static struct regulator *reg_vddio_sdmmc1 = NULL;
@@ -190,12 +186,6 @@ static int __devinit tegra_sdhci_probe(struct platform_device *pdev)
ioaddr = ioremap(res->start, res->end - res->start);
- /* Fix ME: Enable the LVL2 CLK OVR bit */
- ioaddr_clk_rst = ioremap(0x60006300, 0x400);
- val = readl(ioaddr_clk_rst + 0xa0);
- val |= 0x68;
- writel(val, ioaddr_clk_rst + 0xa0);
-
sdhci = sdhci_alloc_host(&pdev->dev, sizeof(struct tegra_sdhci_host));
if (IS_ERR(sdhci)) {
rc = PTR_ERR(sdhci);