diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-10-21 18:59:14 +0800 |
|---|---|---|
| committer | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-10-28 18:55:55 +0800 |
| commit | d390f670990a0880cdd0db4271a724a96755b0ea (patch) | |
| tree | 496077a779bb9ca93e13f203611ec04e4143b872 | |
| parent | cac9eb41debc6444d753dc936cdf76874260b9e4 (diff) | |
MLK-9723-6: ARM: dts: add imx6sx-19x19-arm2-mqs.dts for mqs
Initialize dts file for mqs.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
| -rw-r--r-- | arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts | 41 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 15 |
2 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts new file mode 100644 index 000000000000..a137443d0e88 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-arm2.dts" + +/ { + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + }; +}; + +&esai { + /* pin conflict with sai */ + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs_1>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sdma { + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index f38d8ae839fd..6c446f465fcd 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -563,6 +563,12 @@ reg = <0x020cc000 0x4000>; }; + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "simple-bus"; #address-cells = <1>; @@ -1670,6 +1676,15 @@ }; }; + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + pwm3 { pinctrl_pwm3_0: pwm3grp-0 { fsl,pins = < |