ENGR00125205 mx50: add esdhc3 support

Add IOMUX and configuration data for esdhc3

Signed-off-by: Aisheng.Dong <b29396@freescale.com>

2 files changed, 89 insertions, 4 deletions

diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c
index 11707e459c36..3a4e8dc3e923 100644
--- a/arch/arm/mach-mx5/mx50_arm2.c
+++ b/arch/arm/mach-mx5/mx50_arm2.c
@@ -273,8 +273,10 @@ static int sdhc_write_protect(struct device *dev)
 
 	if (to_platform_device(dev)->id == 0)
 		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0));
-	else
+	else if (to_platform_device(dev)->id == 1)
 		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
+	else if (to_platform_device(dev)->id == 2)
+		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD3_WP));
 
 	return rc;
 }
@@ -284,8 +286,10 @@ static unsigned int sdhc_get_card_det_status(struct device *dev)
 	int ret;
 	if (to_platform_device(dev)->id == 0)
 		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE));
-	else
+	else if (to_platform_device(dev)->id == 1)
 		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_CD));
+	else if (to_platform_device(dev)->id == 2)
+		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2));
 
 	return ret;
 }
@@ -315,6 +319,18 @@ static struct mxc_mmc_platform_data mmc2_data = {
 	.clock_mmc = "esdhc_clk",
 };
 
+static struct mxc_mmc_platform_data mmc3_data = {
+	.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
+		| MMC_VDD_31_32,
+	.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+	.min_clk = 400000,
+	.max_clk = 50000000,
+	.card_inserted_state = 0,
+	.status = sdhc_get_card_det_status,
+	.wp_status = sdhc_write_protect,
+	.clock_mmc = "esdhc_clk",
+};
+
 static int mxc_sgtl5000_amp_enable(int enable)
 {
 /* TO DO */
@@ -456,10 +472,12 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 static void __init mxc_board_init(void)
 {
 	/* SD card detect irqs */
-	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
-	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
 	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE);
 	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE);
+	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
+	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
+	mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2);
+	mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2);
 
 	mxc_cpu_common_init();
 	mxc_register_gpios();
@@ -489,6 +507,7 @@ static void __init mxc_board_init(void)
 
 	mxc_register_device(&mxcsdhc1_device, &mmc1_data);
 	mxc_register_device(&mxcsdhc2_device, &mmc2_data);
+	mxc_register_device(&mxcsdhc3_device, &mmc3_data);
 	mxc_register_device(&mxc_ssi1_device, NULL);
 	mxc_register_device(&mxc_ssi2_device, NULL);
 	mxc_register_device(&mxc_fec_device, &fec_data);
diff --git a/arch/arm/mach-mx5/mx50_arm2_gpio.c b/arch/arm/mach-mx5/mx50_arm2_gpio.c
index d2586d7486f8..975e8967a877 100644
--- a/arch/arm/mach-mx5/mx50_arm2_gpio.c
+++ b/arch/arm/mach-mx5/mx50_arm2_gpio.c
@@ -113,6 +113,64 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0,
 	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
 	 },
+	{		/* SD3 CD */
+	 MX50_PIN_KEY_COL2, IOMUX_CONFIG_GPIO,
+	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+	 },
+	{		/* SD3 WP */
+	 MX50_PIN_SD3_WP, IOMUX_CONFIG_GPIO,
+	 },
+	{		/* SD3 CMD */
+	 MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 CLK */
+	 MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU |
+	 PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D0 */
+	 MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D1 */
+	 MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D2 */
+	 MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D3 */
+	 MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D4 */
+	 MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D5 */
+	 MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D6 */
+	 MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+	{		/* SD3 D7 */
+	 MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
+	 },
+
 	{
 	 MX50_PIN_SSI_TXD, IOMUX_CONFIG_ALT0,
 	 },
@@ -484,6 +542,14 @@ void __init mx50_arm2_io_init(void)
 	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_CD), "sd2_cd");
 	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_CD));
 
+	/* SD3 WP */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), "sd3_wp");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
+
+	/* SD3 CD */
+	gpio_request(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2), "key_col2");
+	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2));
+
 	/* LINE1_DETECT (headphone detect) */
 	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_SS0));