diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-07-07 18:36:50 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:28:15 -0700 |
| commit | c126ff3a0e723c4379a1dc8f68c8f0e369338c13 (patch) | |
| tree | adf0f8f0feb377873030ff2cea4eec107eb020e5 | |
| parent | aef4b0f8f4a1ee3a8d6c1471f7db5818179d4a7c (diff) | |
ARM: tegra: clock: Update Tegra3 PLLE spread settings
Bug 818305
Original-Change-Id: I2560c342c1ad152f1563a29d7a3618c50ded7ef2
Reviewed-on: http://git-master/r/40113
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rec5fdd633170b8dba0ac4236618e503c8b1f761a
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index f71b989fa2ba..c5686072b6d3 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -276,8 +276,8 @@ #define PLLE_SS_COEFFICIENTS_MASK \ (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK) #define PLLE_SS_COEFFICIENTS_12MHZ \ - ((0x1d<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ - (0x29<<PLLE_SS_MAX_SHIFT)) + ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ + (0x24<<PLLE_SS_MAX_SHIFT)) #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10)) #define PLLE_AUX 0x48c |