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authorTony Lin <tony.lin@freescale.com>2011-07-18 13:46:23 +0800
committerNitin Garg <nitin.garg@freescale.com>2014-06-03 20:39:08 -0500
commit08a64fb7cc7a66e4c7cb7b05583b0b441b79d40a (patch)
tree8b797fdcac9838443400a92d5723a12724f63fd8
parent1360820a5196a8f6e7d816f868f7e1a98351f871 (diff)
ENGR00153221 [MX6Q uSDHC]workaround for TC intr coming ealier than DMA intr
if TC interrupt bit is set but DMA interrupt bit is clear, read status register again in case DMA interrupt will come in next time cycle Signed-off-by: Tony Lin <tony.lin@freescale.com>
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 3938955c0605..958a0ed88259 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -99,6 +99,17 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
val |= SDHCI_CARD_PRESENT;
}
+ if (reg == SDHCI_INT_STATUS && cpu_is_mx6q())
+ /*
+ * on mx6q, there is low possibility that
+ * DATA END interrupt comes ealier than DMA
+ * END interrupt which is conflict with standard
+ * host controller spec. In this case, read the
+ * status register again will workaround this issue.
+ */
+ if ((val & SDHCI_INT_DATA_END) && \
+ !(val & SDHCI_INT_DMA_END))
+ val = readl(host->ioaddr + reg);
return val;
}