diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2008-11-10 14:14:11 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2008-11-10 14:14:11 +0000 |
| commit | 8553cb67d2318db327071018fc81084cbabccc46 (patch) | |
| tree | f2db64a188cbf2cce745720bf3d279daa2768609 | |
| parent | 73b63efaac7352c9e2bf1570fac98fd44a99f8f9 (diff) | |
Modern processors may need to drain the WB before WFI
Since WFI may cause the processor to enter a low-power mode, data may
still be in the write buffer. This patch adds a DSB (or DWB) to the
cpu_(v6|v7)_do_idle functions before the WFI.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm/mm/proc-v6.S | 2 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 294943b85973..f0cc599facb7 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -71,6 +71,8 @@ ENTRY(cpu_v6_reset) * IRQs are already disabled. */ ENTRY(cpu_v6_do_idle) + mov r1, #0 + mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt mov pc, lr diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 721b7d53bfd8..0e11d9716a7d 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -63,6 +63,7 @@ ENDPROC(cpu_v7_reset) * IRQs are already disabled. */ ENTRY(cpu_v7_do_idle) + dsb @ WFI may enter a low-power mode wfi mov pc, lr ENDPROC(cpu_v7_do_idle) |