diff options
| author | Fugang Duan <b38611@freescale.com> | 2014-12-10 18:55:04 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-02-18 11:45:23 -0600 |
| commit | 4742c51f570ed863b4fa57b94acfb51c2ab49cff (patch) | |
| tree | 0c39bacc2774789fb8b91d1467dea09a5d08edeb | |
| parent | db54b55f8a30168feb6ecb7de4ac413cbaaec79a (diff) | |
MLK-10199 ARM: clk-imx6q: set enet pll rate to 125Mhzrel_imx_3.10.53_1.1.1
Set enet pll rate to 125Mhz for RGMII tx refrence clock to
support i.MX6q sabreauto cpu2 board.
Signed-off-by: Fugang Duan <B38611@freescale.com>
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 59cda8b89135..7ddf1cc90799 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -752,6 +752,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */ imx_clk_set_rate(clk[pll4_audio_div], 541900800); + /*Set enet_ref clock to 125M to supply for RGMII tx_clk */ + clk_set_rate(clk[enet_ref], 125000000); + #ifdef CONFIG_MX6_VPU_352M /* * If VPU 352M is enabled, then PLL2_PDF2 need to be |