summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorScott Williams <scwilliams@nvidia.com>2012-02-21 17:20:10 -0800
committerSimone Willett <swillett@nvidia.com>2012-02-23 09:40:58 -0800
commitaaae1b3660d8d1c6f0cfe2aeeb510b395a303d44 (patch)
treec22d5f1aa72e4e8ff04687872b47614907bb4e70
parent11a3dbd18fc0a49999879485cce37a06f10e0de9 (diff)
ARM: tegra: Do not unlock CoreSight register access
There is no reason to unlock APB CoreSight register access in the kernel. The debugger can perform it's own unlock operation as needed. Keep the registers write-protected to prevent inadvertent access. Change-Id: I22f28f76b5dd498b3782ab3380a04f865b59d6fd Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/85039 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/headsmp.S10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 4763528a5f16..5bb68433050a 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -49,7 +49,6 @@
*/
ENTRY(tegra_secondary_startup)
bl tegra_invalidate_l1
- bl tegra_enable_coresite
b secondary_startup
ENDPROC(tegra_secondary_startup)
#endif
@@ -63,7 +62,6 @@ ENDPROC(tegra_secondary_startup)
* re-enabling sdram.
*/
ENTRY(tegra_resume)
- bl tegra_enable_coresite
bl tegra_invalidate_l1
cpu_id r0
@@ -134,12 +132,6 @@ tegra_invalidate_l1:
isb
mov pc, lr
- /* Enable Coresight access on cpu */
-tegra_enable_coresite:
- mov32 r0, 0xC5ACCE55
- mcr p14, 0, r0, c7, c12, 6
- mov pc, lr
-
/*
* __tegra_cpu_reset_handler_halt_failed:
*
@@ -172,8 +164,6 @@ ENTRY(__tegra_cpu_reset_handler_start)
ENTRY(__tegra_cpu_reset_handler)
#if DEBUG_CPU_RESET_HANDLER
- mov32 r0, 0xC5ACCE55
- mcr p14, 0, r0, c7, c12, 6 @ Enable CoreSight access
b .
#endif
#ifndef CONFIG_TRUSTED_FOUNDATIONS