diff options
| author | Andi Kleen <ak@suse.de> | 2008-01-30 13:32:41 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-01-30 13:32:41 +0100 |
| commit | 32c7553f824d0d76771404f0e11d6059f82e8de7 (patch) | |
| tree | 12803c3426871f487652b225358a2c0ed7492989 | |
| parent | 51fc97b93545e71cec578d6771bceeb92bc2d50b (diff) | |
x86: remove explicit C3 TSC check on 64bit
Trust the ACPI code to disable TSC instead when C3 is used.
AMD Fam10h does not disable TSC in any C states so the
check was incorrect there anyways after the change
to handle this like Intel on AMD too.
This allows to use the TSC when C3 is disabled in software
(acpi.max_c_state=2), but the BIOS supports it anyways.
Match i386 behaviour.
Cc: lenb@kernel.org
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| -rw-r--r-- | arch/x86/kernel/tsc_64.c | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c index 322b38c68198..c62f3b6eacc0 100644 --- a/arch/x86/kernel/tsc_64.c +++ b/arch/x86/kernel/tsc_64.c @@ -273,15 +273,8 @@ __cpuinit int unsynchronized_tsc(void) return 1; #endif - if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { -#ifdef CONFIG_ACPI - /* But TSC doesn't tick in C3 so don't use it there */ - if (acpi_gbl_FADT.header.length > 0 && - acpi_gbl_FADT.C3latency < 1000) - return 1; -#endif + if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) return 0; - } /* Assume multi socket systems are not synchronized */ return num_present_cpus() > 1; |