diff options
| author | Tony Lin <tony.lin@freescale.com> | 2011-07-18 13:46:23 +0800 |
|---|---|---|
| committer | Tony Lin <tony.lin@freescale.com> | 2011-07-18 13:46:23 +0800 |
| commit | f7292787c187bc01f2a9ca029bfdca21a8406f48 (patch) | |
| tree | 539c353a4ba84f435965d627cc284d241045915a | |
| parent | dc91552e5f2d01e9fb78d88304e2f6f0083c43ff (diff) | |
ENGR00153221 [MX6Q uSDHC]workaround for TC intr coming ealier than DMA intr
if TC interrupt bit is set but DMA interrupt bit is clear, read status register
again in case DMA interrupt will come in next time cycle
Signed-off-by: Tony Lin <tony.lin@freescale.com>
| -rw-r--r-- | drivers/mmc/host/sdhci-esdhc-imx.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 033ed1f777a4..edc2dd692985 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -99,6 +99,17 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val |= SDHCI_CARD_PRESENT; } + if (reg == SDHCI_INT_STATUS && cpu_is_mx6q()) + /* + * on mx6q, there is low possibility that + * DATA END interrupt comes ealier than DMA + * END interrupt which is conflict with standard + * host controller spec. In this case, read the + * status register again will workaround this issue. + */ + if ((val & SDHCI_INT_DATA_END) && \ + !(val & SDHCI_INT_DMA_END)) + val = readl(host->ioaddr + reg); return val; } |