ENGR00122167-3 MSL: add VGA support and fix TVE clock issue.

Fix tve clock tree and adding TVE-VGA support.

Signed-off-by: Jason Chen <b02280@freescale.com>
(cherry picked from commit 0222a76d7798f9a52f7156173e9c66d49384cda6)

3 files changed, 102 insertions, 41 deletions

diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index f726cc06a3e8..746387092106 100644
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -1518,6 +1518,7 @@ static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent)
 	return 0;
 }
 
+static int priv_div;
 static unsigned long _clk_ipu_di_get_rate(struct clk *clk)
 {
 	u32 reg, mux;
@@ -1531,7 +1532,8 @@ static unsigned long _clk_ipu_di_get_rate(struct clk *clk)
 		    MXC_CCM_CDCDR_DI1_CLK_PRED_MASK;
 		div = (reg >> MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET) + 1;
 	} else if ((mux == 3) && (clk->id == 1)) {
-		div = 8;
+		if (priv_div)
+			div = priv_div;
 	} else if ((mux == 3) && (clk->id == 0)) {
 		reg = __raw_readl(MXC_CCM_CDCDR) &
 			MXC_CCM_CDCDR_DI_PLL4_PODF_MASK;
@@ -1563,6 +1565,7 @@ static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate)
 		__raw_writel(reg, MXC_CCM_CDCDR);
 	} else if (((clk->parent == &tve_clk) && (clk->id == 1)) ||
 		((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())) {
+		priv_div = div;
 		return 0;
 	} else
 		return -EINVAL;
@@ -1579,7 +1582,7 @@ static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
 	if ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())
 		return parent_rate;
 	else {
-		div = parent_rate / rate;
+		div = (parent_rate + rate/2) / rate;
 		if (div > 8)
 			div = 8;
 		else if (div == 0)
@@ -1999,7 +2002,7 @@ static unsigned long _clk_tve_round_rate(struct clk *clk,
 	if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL))
 		return -EINVAL;
 
-	div = parent_rate / rate;
+	div = (parent_rate + rate/2) / rate;
 	if (div > 8)
 		div = 8;
 	else if (div == 0)
@@ -2031,27 +2034,6 @@ static int _clk_tve_set_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
-static int _clk_tve_enable(struct clk *clk)
-{
-	_clk_enable(clk);
-	if (clk_get_parent(&ipu_di_clk[1]) != clk) {
-		clk_enable(&ipu_di_clk[1]);
-		ipu_di_clk[1].set_parent(&ipu_di_clk[1], clk);
-		ipu_di_clk[1].parent = clk;
-	}
-	return 0;
-}
-
-static void _clk_tve_disable(struct clk *clk)
-{
-	_clk_disable(clk);
-	if (clk_get_parent(&ipu_di_clk[1]) == clk) {
-		ipu_di_clk[1].set_parent(&ipu_di_clk[1], &pll3_sw_clk);
-		ipu_di_clk[1].parent = &pll3_sw_clk;
-		clk_disable(&ipu_di_clk[1]);
-	}
-}
-
 static struct clk tve_clk = {
 	.parent = &pll3_sw_clk,
 	.set_parent = _clk_tve_set_parent,
@@ -2060,8 +2042,8 @@ static struct clk tve_clk = {
 	.get_rate = _clk_tve_get_rate,
 	.round_rate = _clk_tve_round_rate,
 	.set_rate = _clk_tve_set_rate,
-	.enable = _clk_tve_enable,
-	.disable = _clk_tve_disable,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
 	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
@@ -4249,7 +4231,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "ipu_di1_clk", ipu_di_clk[1]),
 	_REGISTER_CLOCK(NULL, "csi_mclk1", csi0_clk),
 	_REGISTER_CLOCK(NULL, "csi_mclk2", csi1_clk),
-	_REGISTER_CLOCK("tve.0", NULL, tve_clk),
+	_REGISTER_CLOCK(NULL, "tve_clk", tve_clk),
 	_REGISTER_CLOCK("mxcintuart.0", NULL, uart1_clk[0]),
 	_REGISTER_CLOCK("mxcintuart.1", NULL, uart2_clk[0]),
 	_REGISTER_CLOCK("mxcintuart.2", NULL, uart3_clk[0]),
diff --git a/arch/arm/mach-mx5/mx53_evk.c b/arch/arm/mach-mx5/mx53_evk.c
index 6cf08f17426e..5ea882ef4adb 100644
--- a/arch/arm/mach-mx5/mx53_evk.c
+++ b/arch/arm/mach-mx5/mx53_evk.c
@@ -449,13 +449,24 @@ static struct fb_videomode video_modes[] = {
 	 FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
 	 0,},
 	{
-	 "720P60", 60, 1280, 720, 13468,
-	 260, 109,
-	 25, 4,
-	 1, 1,
+	 /* 1080i50 TV output */
+	 "1080I50", 50, 1920, 1080, 13468,
+	 148, 528,
+	 36, 4,
+	 44, 5,
 	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
 			FB_SYNC_EXT,
-	 FB_VMODE_NONINTERLACED,
+	 FB_VMODE_INTERLACED,
+	 0,},
+	{
+	 /* 1080i60 TV output */
+	 "1080I60", 60, 1920, 1080, 13468,
+	 148, 88,
+	 36, 4,
+	 44, 5,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+			FB_SYNC_EXT,
+	 FB_VMODE_INTERLACED,
 	 0,},
 	{
 	 /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
@@ -464,6 +475,51 @@ static struct fb_videomode video_modes[] = {
 	 FB_VMODE_NONINTERLACED,
 	 0,},
 	{
+	/* VGA 1024x768 65M pixel clk output */
+	"VGA-XGA", 60, 1024, 768, 15384,
+	24, 160,
+	3, 29,
+	136, 6,
+	FB_SYNC_EXT,
+	FB_VMODE_NONINTERLACED,
+	0,},
+	{
+	 "XGA", 60, 1024, 768, 15385,
+	 220, 40,
+	 21, 7,
+	 60, 10,
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* 720p30 TV output */
+	 "720P30", 30, 1280, 720, 13468,
+	 256, 1760,
+	 20, 5,
+	 4, 5,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 "720P60", 60, 1280, 720, 13468,
+	 260, 109,
+	 25, 4,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+			FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	/* VGA 1280x1024 108M pixel clk output */
+	"SXGA", 60, 1280, 1024, 9259,
+	48, 248,
+	1, 38,
+	112, 3,
+	FB_SYNC_EXT,
+	FB_VMODE_NONINTERLACED,
+	0,},
+	{
 	/* 1600x1200 @ 60 Hz 162M pixel clk*/
 	"UXGA", 60, 1600, 1200, 6172,
 	304, 64,
@@ -474,18 +530,40 @@ static struct fb_videomode video_modes[] = {
 	FB_VMODE_NONINTERLACED,
 	0,},
 	{
-	 "1080P60", 60, 1920, 1080, 7692,
-	 100, 40,
-	 30, 3,
-	 10, 2,
+	 /* 1080p24 TV output */
+	 "1080P24", 24, 1920, 1080, 13468,
+	 148, 638,
+	 36, 4,
+	 44, 5,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
 	 FB_SYNC_EXT,
 	 FB_VMODE_NONINTERLACED,
 	 0,},
 	{
-	 "XGA", 60, 1024, 768, 15385,
-	 220, 40,
-	 21, 7,
-	 60, 10,
+	 /* 1080p25 TV output */
+	 "1080P25", 25, 1920, 1080, 13468,
+	 148, 528,
+	 36, 4,
+	 44, 5,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 /* 1080p30 TV output */
+	 "1080P30", 30, 1920, 1080, 13468,
+	 148, 88,
+	 36, 4,
+	 44, 5,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+	{
+	 "1080P60", 60, 1920, 1080, 7692,
+	 100, 40,
+	 30, 3,
+	 10, 2,
 	 FB_SYNC_EXT,
 	 FB_VMODE_NONINTERLACED,
 	 0,},
@@ -826,7 +904,7 @@ static struct mxc_fb_platform_data fb_data[] = {
 	 .num_modes = ARRAY_SIZE(video_modes),
 	 },
 	{
-	 .interface_pix_fmt = IPU_PIX_FMT_BGR24,
+	 .interface_pix_fmt = IPU_PIX_FMT_GBR24,
 	 .mode_str = "1024x768M-16@60",
 	 .mode = video_modes,
 	 .num_modes = ARRAY_SIZE(video_modes),
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 26c09dd6b05c..a95e781164ec 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -384,6 +384,7 @@ typedef enum iomux_config {
 #define MX53_PAD_EIM_A25__DI0_D1_CS		IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_OE__DI1_PIN7			IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_RW__DI1_PIN8			IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__DI1_PIN15		IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D21__DISPB0_SER_CLK		IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D22__DISPB0_SER_DIN		IOMUX_PAD(0x478, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_CSI0_D4__CSI0_D4		IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, \