ENGR00152845-3 MSL imx6: msl files changes.

imx6 MSL files change, include clock change for ipu.

Signed-off-by: Jason Chen <jason.chen@freescale.com>

6 files changed, 162 insertions, 43 deletions

diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index f07f22bd0c6e..ab563e91ba57 100644
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -8,6 +8,9 @@ config ARCH_MX6Q
 	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_FEC
 	select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL
+	select IMX_HAVE_PLATFORM_IMX_IPUV3
+	select IMX_HAVE_PLATFORM_MXC_PWM
+	select IMX_HAVE_PLATFORM_LDB
 
 config FORCE_MAX_ZONEORDER
     int "MAX_ORDER"
diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index 9791f676f7e0..0baf7b466699 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -58,6 +58,7 @@
 #include <mach/imx-uart.h>
 #include <mach/viv_gpu.h>
 #include <mach/ahci_sata.h>
+#include <mach/ipu-v3.h>
 #include <linux/gpio.h>
 #include <linux/etherdevice.h>
 
@@ -65,8 +66,10 @@
 #include "devices-imx6q.h"
 #include "crm_regs.h"
 
+#define MX6Q_SABREAUTO_LDB_BACKLIGHT	IMX_GPIO_NR(1, 9)
 #define MX6Q_SABREAUTO_ECSPI1_CS0	IMX_GPIO_NR(2, 30)
 #define MX6Q_SABREAUTO_ECSPI1_CS1	IMX_GPIO_NR(3, 19)
+#define MX6Q_SABREAUTO_DISP0_PWR	IMX_GPIO_NR(3, 24)
 #define MX6Q_SABREAUTO_SD3_CD	IMX_GPIO_NR(6, 11)
 #define MX6Q_SABREAUTO_SD3_WP	IMX_GPIO_NR(6, 14)
 #define MX6Q_SABREAUTO_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
@@ -152,6 +155,41 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = {
 	MX6Q_PAD_KEY_COL3__I2C2_SCL,
 	MX6Q_PAD_KEY_ROW3__I2C2_SDA,
 
+	/* DISPLAY */
+	MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+	MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+	MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+	MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+	MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+	MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+	MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+	MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+	MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+	MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+	MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+	MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+	MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+	MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+	MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+	MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+	MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+	MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+	MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+	MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+	MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+	MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+	MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+	MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+	MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+	MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+	MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+	MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+
+	MX6Q_PAD_EIM_D24__GPIO_3_24,
+
+	/* ldb: pwm fixme*/
+	MX6Q_PAD_GPIO_9__GPIO_1_9,
+
 	/* I2C3 */
 	MX6Q_PAD_GPIO_5__I2C3_SCL,
 	MX6Q_PAD_GPIO_16__I2C3_SDA,
@@ -387,15 +425,64 @@ static struct ahci_platform_data mx6q_sabreauto_sata_data = {
 	.exit = mx6q_sabreauto_sata_exit,
 };
 
+static struct ipuv3_fb_platform_data sabr_fb_data[] = {
+	{ /*fb0*/
+	.disp_dev = "lcd",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB565,
+	.mode_str = "CLAA-WVGA",
+	.default_bpp = 16,
+	.int_clk = false,
+	}, {
+	.disp_dev = "ldb",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
+	.mode_str = "LDB-XGA",
+	.default_bpp = 16,
+	.int_clk = false,
+	},
+};
+
+static struct fsl_mxc_lcd_platform_data lcdif_data = {
+	.ipu_id = 0,
+	.disp_id = 0,
+	.default_ifmt = IPU_PIX_FMT_RGB565,
+};
+
+static struct fsl_mxc_ldb_platform_data ldb_data = {
+	.ipu_id = 1,
+	.disp_id = 0,
+	.ext_ref = 1,
+	.mode = LDB_SEP,
+};
+
+static struct imx_ipuv3_platform_data ipu_data[] = {
+	{
+	.rev = 4,
+	}, {
+	.rev = 4,
+	},
+};
+
 /*!
  * Board specific initialization.
  */
 static void __init mx6_board_init(void)
 {
+	int i;
+
 	mxc_iomux_v3_setup_multiple_pads(mx6q_sabreauto_pads,
 					ARRAY_SIZE(mx6q_sabreauto_pads));
 
 	mx6q_sabreauto_init_uart();
+
+	imx6q_add_ipuv3(0, &ipu_data[0]);
+	imx6q_add_ipuv3(1, &ipu_data[1]);
+
+	for (i = 0; i < ARRAY_SIZE(sabr_fb_data); i++)
+		imx6q_add_ipuv3fb(i, &sabr_fb_data[i]);
+
+	imx6q_add_lcdif(&lcdif_data);
+	imx6q_add_ldb(&ldb_data);
+	imx6q_add_v4l2_output(0);
 	imx6q_add_imx_i2c(1, &mx6q_sabreauto_i2c_data);
 	imx6q_add_imx_i2c(2, &mx6q_sabreauto_i2c_data);
 	i2c_register_board_info(2, mxc_i2c2_board_info,
@@ -410,6 +497,12 @@ static void __init mx6_board_init(void)
 	imx_add_viv_gpu("gc320", &imx6_gc320_data, NULL);
 	imx6q_sabreauto_init_usb();
 	imx6q_add_ahci(0, &mx6q_sabreauto_sata_data);
+
+	gpio_request(MX6Q_SABREAUTO_DISP0_PWR, "disp0-pwr");
+	gpio_direction_output(MX6Q_SABREAUTO_DISP0_PWR, 1);
+
+	gpio_request(MX6Q_SABREAUTO_LDB_BACKLIGHT, "ldb-backlight");
+	gpio_direction_output(MX6Q_SABREAUTO_LDB_BACKLIGHT, 1);
 }
 
 extern void __iomem *twd_base;
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 3f20e453bbd7..218ed86b476c 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -244,10 +244,12 @@ static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 	u64 tmp;
 
 	tmp = (u64)clk_get_rate(clk->parent) * 18;
+	tmp += rate/2;
 	do_div(tmp, rate);
 	frac = tmp;
-	frac = frac < 18 ? 18 : frac;
+	frac = frac < 12 ? 12 : frac;
 	frac = frac > 35 ? 35 : frac;
+	tmp = (u64)clk_get_rate(clk->parent) * 18;
 	do_div(tmp, frac);
 	return tmp;
 }
@@ -2390,9 +2392,10 @@ static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
 		(clk->parent == &ldb_di1_clk))
 		return clk_get_rate(clk->parent);
 
-	reg = __raw_readl(MXC_CCM_CHSCCDR);
+	reg = __raw_readl(MXC_CCM_CSCDR2);
 
-	div = (reg & MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK) + 1;
+	div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
+			MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
 
 	return clk_get_rate(clk->parent) / div;
 }
@@ -2416,10 +2419,10 @@ static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
 	if (((parent_rate / div) != rate) || (div > 8))
 		return -EINVAL;
 
-	reg = __raw_readl(MXC_CCM_CHSCCDR);
-	reg &= ~MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CHSCCDR);
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR2);
 
 	return 0;
 }
@@ -2433,23 +2436,23 @@ static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
 	else if (parent == &ldb_di1_clk)
 		mux = 0x4;
 	else {
-		reg = __raw_readl(MXC_CCM_CHSCCDR)
-			& ~MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK;
+		reg = __raw_readl(MXC_CCM_CSCDR2)
+			& ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
 
 		mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
 				&pll3_usb_otg_main_clk, &pll5_video_main_clk,
 				&pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
-		reg |= (mux << MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET);
+		reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
 
-		__raw_writel(reg, MXC_CCM_CHSCCDR);
+		__raw_writel(reg, MXC_CCM_CSCDR2);
 
 		/* Derive clock from divided pre-muxed ipu2_di0 clock.*/
 		mux = 0;
 	}
-	reg = __raw_readl(MXC_CCM_CHSCCDR)
-		& ~MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK;
-	__raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET),
-		MXC_CCM_CHSCCDR);
+	reg = __raw_readl(MXC_CCM_CSCDR2)
+		& ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
+	__raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
+		MXC_CCM_CSCDR2);
 
 	return 0;
 }
@@ -2462,9 +2465,10 @@ static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
 		(clk->parent == &ldb_di1_clk))
 		return clk_get_rate(clk->parent);
 
-	reg = __raw_readl(MXC_CCM_CHSCCDR);
+	reg = __raw_readl(MXC_CCM_CSCDR2);
 
-	div = (reg & MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK) + 1;
+	div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
+		>> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
 
 	return clk_get_rate(clk->parent) / div;
 }
@@ -2488,10 +2492,10 @@ static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
 	if (((parent_rate / div) != rate) || (div > 8))
 		return -EINVAL;
 
-	reg = __raw_readl(MXC_CCM_CHSCCDR);
-	reg &= ~MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET;
-	__raw_writel(reg, MXC_CCM_CHSCCDR);
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR2);
 
 	return 0;
 }
@@ -2505,23 +2509,23 @@ static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
 	else if (parent == &ldb_di1_clk)
 		mux = 0x4;
 	else {
-		reg = __raw_readl(MXC_CCM_CHSCCDR)
-			& ~MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK;
+		reg = __raw_readl(MXC_CCM_CSCDR2)
+			& ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
 
 		mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
 				&pll3_usb_otg_main_clk, &pll5_video_main_clk,
 				&pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
-		reg |= (mux << MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET);
+		reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
 
-		__raw_writel(reg, MXC_CCM_CHSCCDR);
+		__raw_writel(reg, MXC_CCM_CSCDR2);
 
 		/* Derive clock from divided pre-muxed ipu1_di0 clock.*/
 		mux = 0;
 	}
-	reg = __raw_readl(MXC_CCM_CHSCCDR)
-		& ~MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK;
-	__raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET),
-		MXC_CCM_CHSCCDR);
+	reg = __raw_readl(MXC_CCM_CSCDR2)
+		& ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
+	__raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
+		MXC_CCM_CSCDR2);
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h
index e436ccfc8baa..d53e0eaeab89 100644
--- a/arch/arm/mach-mx6/crm_regs.h
+++ b/arch/arm/mach-mx6/crm_regs.h
@@ -12,7 +12,7 @@
 #define __ARCH_ARM_MACH_MX6_CRM_REGS_H__
 
 /* IOMUXC */
-#define MXC_IOMUXC_BASE			MX6_IO_ADDRESS(IOMUXC_BASE_ADDR)
+#define MXC_IOMUXC_BASE			MX6_IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR)
 #define IOMUXC_GPR0			(MXC_IOMUXC_BASE + 0x00)
 #define IOMUXC_GPR1			(MXC_IOMUXC_BASE + 0x04)
 #define IOMUXC_GPR2			(MXC_IOMUXC_BASE + 0x08)
@@ -347,18 +347,18 @@
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		(19)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	(15)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK		(0x7 << 12)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET		(12)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK		(0x7 << 9)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET		(9)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET	(6)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK		(0x7 << 3)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET		(3)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK		(0x7)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET		(0)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET	(15)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET		(12)
+#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET		(9)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET	(6)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET		(3)
+#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK		(0x7)
+#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET		(0)
 
 /* Define the bits in register CSCDR3 */
 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK		(0x7 << 16)
diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
index ca2fbb59b312..283a24299da5 100644
--- a/arch/arm/mach-mx6/devices-imx6q.h
+++ b/arch/arm/mach-mx6/devices-imx6q.h
@@ -76,3 +76,22 @@ extern const struct imx_viv_gpu_data imx6_gc355_data __initconst;
 extern const struct imx_ahci_data imx6q_ahci_data __initconst;
 #define imx6q_add_ahci(id, pdata)   \
 	imx_add_ahci(&imx6q_ahci_data, pdata)
+extern const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst;
+#define imx6q_add_ipuv3(id, pdata)	imx_add_ipuv3(id, &imx6q_ipuv3_data[id], pdata)
+#define imx6q_add_ipuv3fb(id, pdata)	imx_add_ipuv3_fb(id, pdata)
+
+#define imx6q_add_lcdif(pdata)	\
+	platform_device_register_resndata(NULL, "mxc_lcdif",\
+			0, NULL, 0, pdata, sizeof(*pdata));
+
+extern const struct imx_ldb_data imx6q_ldb_data __initconst;
+#define imx6q_add_ldb(pdata) \
+	imx_add_ldb(&imx6q_ldb_data, pdata);
+
+#define imx6q_add_v4l2_output(id)	\
+	platform_device_register_resndata(NULL, "mxc_v4l2_output",\
+			id, NULL, 0, NULL, 0);
+
+#define imx6q_add_v4l2_capture(id)	\
+	platform_device_register_resndata(NULL, "mxc_v4l2_capture",\
+			id, NULL, 0, NULL, 0);
diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c
index 9d5bbf633230..124144d61dce 100644
--- a/arch/arm/mach-mx6/mm.c
+++ b/arch/arm/mach-mx6/mm.c
@@ -60,7 +60,7 @@ static struct map_desc mx6_io_desc[] __initdata = {
 void __init mx6_map_io(void)
 {
 	iotable_init(mx6_io_desc, ARRAY_SIZE(mx6_io_desc));
-	mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
+	mxc_iomux_v3_init(IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(IO_ADDRESS(WDOG1_BASE_ADDR));
 }
 #ifdef CONFIG_CACHE_L2X0