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authorNishanth Menon <nm@ti.com>2014-10-21 09:30:46 -0500
committerTony Lindgren <tony@atomide.com>2014-11-10 14:27:35 -0800
commit829acd07793538cbb19ee416e8917d7560fa47c8 (patch)
tree948e55df288e9af05954bb8790a6b4ee4f838193
parent7a15c8e74737283e9c195742074812aeaea08eaa (diff)
ARM: dts: dra72-evm: Provide explicit pinmux for TPS PMIC
Even thought sys_nirq1 is hardwired on the SoC for the pin, it is better to configure the pin to the required mux configuration. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index b135aab0aa5f..5d26fa1144e3 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -65,6 +65,12 @@
0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
+
+ tps65917_pins_default: tps65917_pins_default {
+ pinctrl-single,pins = <
+ 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+ >;
+ };
};
&i2c1 {
@@ -77,6 +83,9 @@
compatible = "ti,tps65917";
reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps65917_pins_default>;
+
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-parent = <&gic>;
interrupt-controller;