diff options
author | Tony Wu <tung7970@gmail.com> | 2013-06-21 10:09:23 +0000 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-07-01 15:10:57 +0200 |
commit | 42a111797e8fa961d6168922e873d6b4be87e904 (patch) | |
tree | 9341504431df162b918307e1c8f52b584f4427d3 | |
parent | fc192e50f868d8f34b15a18c38407f4b9468a31d (diff) |
MIPS: Fix typos and cleanup comment
Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5535/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/include/asm/gic.h | 2 | ||||
-rw-r--r-- | arch/mips/kernel/process.c | 3 | ||||
-rw-r--r-- | arch/mips/mm/tlbex.c | 2 |
3 files changed, 2 insertions, 5 deletions
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 7153b32de18e..b2e3e93dd7d8 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -347,7 +347,7 @@ struct gic_shared_intr_map { #define GIC_CPU_INT2 2 /* . */ #define GIC_CPU_INT3 3 /* . */ #define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ +#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ /* Local GIC interrupts. */ #define GIC_INT_TMR (GIC_CPU_INT5) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 7d62894f7e23..ddc76103e78c 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -207,9 +207,6 @@ unsigned long __stack_chk_guard __read_mostly; EXPORT_SYMBOL(__stack_chk_guard); #endif -/* - * - */ struct mips_frame_info { void *func; unsigned long func_size; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4712f3cd73b7..357e0fd65e94 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -972,7 +972,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) uasm_i_srl(p, ptr, ptr, 19); #else /* - * smp_processor_id() << 3 is stored in CONTEXT. + * smp_processor_id() << 2 is stored in CONTEXT. */ uasm_i_mfc0(p, ptr, C0_CONTEXT); UASM_i_LA_mostly(p, tmp, pgdc); |