diff options
| author | Jason Chen <b02280@freescale.com> | 2011-03-30 17:37:33 +0800 |
|---|---|---|
| committer | Jason Chen <b02280@freescale.com> | 2011-03-31 17:12:43 +0800 |
| commit | a52fde5acdec2fef599130246eb037204db38f3e (patch) | |
| tree | 958083535c2b23771db6f158ff43efbd400a1369 | |
| parent | c0b2882d78ebf70af66694be2efb6535c96d812c (diff) | |
ENGR00141363 ARM imx53 clock: change di0 clock default parent to pll3
If enable both LVDS and one display device use external di clock, there will
be conflict between their clock parent -- both use pll4 on mx53. So it need
change di0 clock parent to pll3, and then uart parent need change to pll2 to
avoid console mess.
Signed-off-by: Jason Chen <b02280@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/clock.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index e15eae3591a7..b940e017614d 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -4958,8 +4958,6 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]); clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk); - clk_set_parent(&ipu_di_clk[0], &pll4_sw_clk); - #if 0 /*Setup the LPM bypass bits */ reg = __raw_readl(MXC_CCM_CLPCR); @@ -5068,7 +5066,6 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&arm_axi_clk, &axi_b_clk); clk_set_parent(&ipu_clk[0], &axi_b_clk); - clk_set_parent(&uart_main_clk, &pll3_sw_clk); clk_set_parent(&gpu3d_clk[0], &axi_b_clk); clk_set_parent(&gpu2d_clk, &axi_b_clk); |