diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-29 14:46:02 -0500 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-09-05 13:12:33 +0800 |
| commit | 7dd230de8f0a238e69df754cd0fe45c8681fc78d (patch) | |
| tree | 541aeffb172ae2edef536bdeffe9d46163757b32 | |
| parent | 963285ae38077768f0e342e00e246a64abd8f315 (diff) | |
ENGR00221974 MX6SL-Fix system hang/crash issue in low power IDLE
Ensure that the pull-up is enabled when the DQS line of LPDDR2
is floated when DDR freq is dropped to 24MHz. This is required
else its possible that the DDR will latch incorrect data when it
exits self-refresh.
CKE line should not be floated as it may cause DDR to incorrectly
exit self-refresh mode.
Also add 25 nops after the code that removes DDR from self-refresh.
We need this to ensure that the prefetcher block in A9 does not
access any instruction from DDR before the DDR exits self-refresh.
The A9 prefetch depth is about 23, hence 25 nops.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/mx6sl_wfi.S | 44 |
1 files changed, 43 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S index d2d910383cb7..89fe4e292352 100644 --- a/arch/arm/mach-mx6/mx6sl_wfi.S +++ b/arch/arm/mach-mx6/mx6sl_wfi.S @@ -109,6 +109,13 @@ str r4, [r1, #0x314] /* DRAM_DQM2 */ str r4, [r1, #0x318] /* DRAM_DQM3 */ + /* Make sure the Pull Ups are enabled. + * So only reduce the drive stength, but + * leave the pull-ups in the original state. + * This is required for LPDDR2. + */ + ldr r4, [r1, #0x344] + orr r4, r4, #0x3000 str r4, [r1, #0x344] /* DRAM_SDQS0 */ str r4, [r1, #0x348] /* DRAM_SDQS1 */ str r4, [r1, #0x34c] /* DRAM_SDQS2 */ @@ -129,7 +136,6 @@ str r4, [r1, #0x33c] /* DRAM_SODT0*/ str r4, [r1, #0x340] /* DRAM_SODT1*/ - str r4, [r1, #0x5c8] /* GPR_CTLDS */ mov r4, #0x80000 str r4, [r1, #0x320] /* DRAM_RESET */ mov r4, #0x1000 @@ -348,6 +354,42 @@ poll_dvfs_clear_1: cmp r6, #0x2000000 beq poll_dvfs_clear_1 + /* Add these nops so that the + * prefetcher will not try to get + * any instructions from DDR. + * The prefetch depth is about 23 + * on A9, so adding 25 nops. + */ + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + /* Enable Automatic power savings. */ ldr r6, [r8, #0x404] bic r6, r6, #0x01 |