diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-11-11 10:16:57 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:36 +0800 |
| commit | 0e98761734b65141302c19c85c0b03ed0b8f6515 (patch) | |
| tree | 06a88fb27bf4c29519ef7ef27baf90c66cea1883 | |
| parent | 672cfd49a3460d0464991cef4e5ee5337ee55a51 (diff) | |
arm64: imx8-ss-dc0.dtsi: Add dc0_dpr1_channel3 and dc0_dpr2_channel1-3 phandles for dpu1
This patch adds dc0_dpr1_channel3 and dc0_dpr2_channel1-3 phandles for dpu1
node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi index 506f5cc210ea..7ce6d50e2db3 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -466,7 +466,11 @@ dc0_subsys: bus@56000000 { <&pd IMX_SC_R_DC_0_PLL_1>; power-domain-names = "dc", "pll0", "pll1"; fsl,dpr-channels = <&dc0_dpr1_channel1>, - <&dc0_dpr1_channel2>; + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; status = "disabled"; }; }; |