diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2010-03-09 09:55:10 +0000 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2010-10-06 16:26:32 -0700 |
| commit | 0ec7f7e47cf5406abbf87da3cd4c556da0f1dcbc (patch) | |
| tree | b7b37de11bf56761976ba306ee0492039ab45633 | |
| parent | 771f2628641969b7fb71f7aa04495943016742bc (diff) | |
Add "nol2x0" early param to avoid initialisation of the L2 controller
Some development platforms may have issues with this controller, so
allow easy disabling from the kernel command line. The patch also adds
a check for l2x0_disabled in the realview_pbx.c code to avoid setting
additional L2x0 registers.
Change-Id: Icbbd3e054688811200a4c96bf7e0a81c9c0ab790
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-realview/realview_pbx.c | 2 | ||||
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 19 |
3 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 89e2ff8a3585..787c06ada555 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -59,6 +59,7 @@ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); extern void l2x0_shutdown(void); extern void l2x0_restart(void); +extern bool l2x0_disabled; #endif #endif diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 9428eff0b116..af13eb6e553c 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -382,7 +382,7 @@ static void __init realview_pbx_init(void) int i; #ifdef CONFIG_CACHE_L2X0 - if (core_tile_pbxa9mp()) { + if (!l2x0_disabled && core_tile_pbxa9mp()) { void __iomem *l2x0_base = __io_address(REALVIEW_PBX_TILE_L220_BASE); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 9eb79d84b460..9abfa5d2b750 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -27,6 +27,7 @@ static void __iomem *l2x0_base; static uint32_t l2x0_way_mask; /* Bitmask of active ways */ +bool l2x0_disabled; static inline void cache_wait_always(void __iomem *reg, unsigned long mask) { @@ -249,6 +250,9 @@ void l2x0_shutdown(void) { unsigned long flags; + if (l2x0_disabled) + return; + BUG_ON(num_online_cpus() > 1); local_irq_save(flags); @@ -282,6 +286,9 @@ static void l2x0_enable(__u32 aux_val, __u32 aux_mask) int ways; const char *type; + if (l2x0_disabled) + return; + cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); @@ -338,6 +345,11 @@ void l2x0_restart(void) void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { + if (l2x0_disabled) { + pr_info(L2CC_TYPE " cache controller disabled\n"); + return; + } + l2x0_base = base; l2x0_enable(aux_val, aux_mask); @@ -347,3 +359,10 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.flush_range = l2x0_flush_range; outer_cache.sync = l2x0_cache_sync; } + +static int __init l2x0_disable(char *unused) +{ + l2x0_disabled = 1; + return 0; +} +early_param("nol2x0", l2x0_disable); |