arch: arm: tegratab: add tegratab support

Create initial board files for Tegratab

bug 1262450
bug 1262648

Change-Id: Ic1049e8be7c77f7f41f8db6ddc3f6643e1dd6914
Signed-off-by: Jake Park <jakep@nvidia.com>
Reviewed-on: http://git-master/r/215438
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

17 files changed, 6660 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/tegra114-tegratab.dts b/arch/arm/boot/dts/tegra114-tegratab.dts
new file mode 100644
index 000000000000..53966f52dd1f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-tegratab.dts
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+/include/ "tegra114.dtsi"
+
+/ {
+	model = "NVIDIA Tegra114 tegratab evaluation board";
+	compatible = "nvidia,tegratab", "nvidia,tegra114";
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			clk1_out_pw4 {
+				nvidia,pins = "clk1_out_pw4";
+				nvidia,function = "extperiph1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			dap1_din_pn1 {
+				nvidia,pins = "dap1_din_pn1";
+				nvidia,function = "i2s0";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			dap1_dout_pn2 {
+				nvidia,pins = "dap1_dout_pn2",
+						"dap1_fs_pn0",
+						"dap1_sclk_pn3";
+				nvidia,function = "i2s0";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			dap2_din_pa4 {
+				nvidia,pins = "dap2_din_pa4";
+				nvidia,function = "i2s1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			dap2_dout_pa5 {
+				nvidia,pins = "dap2_dout_pa5",
+						"dap2_fs_pa2",
+						"dap2_sclk_pa3";
+				nvidia,function = "i2s1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			dap4_din_pp5 {
+				nvidia,pins = "dap4_din_pp5",
+						"dap4_dout_pp6",
+						"dap4_fs_pp4",
+						"dap4_sclk_pp7";
+				nvidia,function = "i2s3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			dvfs_pwm_px0 {
+				nvidia,pins = "dvfs_pwm_px0",
+						"dvfs_clk_px2";
+				nvidia,function = "cldvfs";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			ulpi_clk_py0 {
+				nvidia,pins = "ulpi_clk_py0",
+						"ulpi_data0_po1",
+						"ulpi_data1_po2",
+						"ulpi_data2_po3",
+						"ulpi_data3_po4",
+						"ulpi_data4_po5",
+						"ulpi_data5_po6",
+						"ulpi_data6_po7",
+						"ulpi_data7_po0";
+				nvidia,function = "ulpi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			ulpi_dir_py1 {
+				nvidia,pins = "ulpi_dir_py1",
+						"ulpi_nxt_py2";
+				nvidia,function = "ulpi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			ulpi_stp_py3 {
+				nvidia,pins = "ulpi_stp_py3";
+				nvidia,function = "ulpi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			cam_i2c_scl_pbb1 {
+				nvidia,pins = "cam_i2c_scl_pbb1",
+						"cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+				nvidia,open-drain = <0>;
+			};
+			cam_mclk_pcc0 {
+				nvidia,pins = "cam_mclk_pcc0",
+						"pbb0";
+				nvidia,function = "vi_alt3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+				nvidia,lock = <0>;
+			};
+			gen2_i2c_scl_pt5 {
+				nvidia,pins = "gen2_i2c_scl_pt5",
+						"gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+				nvidia,open-drain = <0>;
+			};
+			gmi_a16_pj7 {
+				nvidia,pins = "gmi_a16_pj7";
+				nvidia,function = "uartd";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gmi_a17_pb0 {
+				nvidia,pins = "gmi_a17_pb0",
+						"gmi_a18_pb1";
+				nvidia,function = "uartd";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			gmi_a19_pk7 {
+				nvidia,pins = "gmi_a19_pk7";
+				nvidia,function = "uartd";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gmi_ad5_pg5 {
+				nvidia,pins = "gmi_ad5_pg5",
+						"gmi_cs6_n_pi3",
+						"gmi_wr_n_pi0";
+				nvidia,function = "spi4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gmi_ad6_pg6 {
+				nvidia,pins = "gmi_ad6_pg6",
+						"gmi_ad7_pg7";
+				nvidia,function = "spi4";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gmi_ad12_ph4 {
+				nvidia,pins = "gmi_ad12_ph4";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gmi_ad9_ph1 {
+				nvidia,pins = "gmi_ad9_ph1";
+				nvidia,function = "pwm1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gmi_cs1_n_pj2 {
+				nvidia,pins = "gmi_cs1_n_pj2",
+						"gmi_oe_n_pi1";
+				nvidia,function = "soc";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			clk2_out_pw5 {
+				nvidia,pins = "clk2_out_pw5";
+				nvidia,function = "extperiph2";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			sdmmc1_cmd_pz1 {
+				nvidia,pins = "sdmmc1_cmd_pz1",
+						"sdmmc1_dat0_py7",
+						"sdmmc1_dat1_py6",
+						"sdmmc1_dat2_py5",
+						"sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			sdmmc1_wp_n_pv3 {
+				nvidia,pins = "sdmmc1_wp_n_pv3";
+				nvidia,function = "spi4";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			sdmmc3_clk_pa6 {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			sdmmc3_cmd_pa7 {
+				nvidia,pins = "sdmmc3_cmd_pa7",
+						"sdmmc3_dat0_pb7",
+						"sdmmc3_dat1_pb6",
+						"sdmmc3_dat2_pb5",
+						"sdmmc3_dat3_pb4",
+						"kb_col4_pq4",
+						"sdmmc3_clk_lb_out_pee4",
+						"sdmmc3_clk_lb_in_pee5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			sdmmc4_clk_pcc4 {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			sdmmc4_cmd_pt7 {
+				nvidia,pins = "sdmmc4_cmd_pt7",
+						"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			clk_32k_out_pa0 {
+				nvidia,pins = "clk_32k_out_pa0";
+				nvidia,function = "blink";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			kb_col0_pq0 {
+				nvidia,pins = "kb_col0_pq0",
+						"kb_col1_pq1",
+						"kb_col2_pq2",
+						"kb_row0_pr0",
+						"kb_row1_pr1",
+						"kb_row2_pr2";
+				nvidia,function = "kbc";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			dap3_din_pp1 {
+				nvidia,pins = "dap3_din_pp1",
+						"dap3_sclk_pp3";
+				nvidia,function = "displayb";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <0>;
+			};
+			pv0 {
+				nvidia,pins = "pv0";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <0>;
+			};
+			kb_row7_pr7 {
+				nvidia,pins = "kb_row7_pr7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			kb_row10_ps2 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "uarta";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			kb_row9_ps1 {
+				nvidia,pins = "kb_row9_ps1";
+				nvidia,function = "uarta";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			pwr_i2c_scl_pz6 {
+				nvidia,pins = "pwr_i2c_scl_pz6",
+						"pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+				nvidia,open-drain = <0>;
+			};
+			sys_clk_req_pz5 {
+				nvidia,pins = "sys_clk_req_pz5";
+				nvidia,function = "sysclk";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			core_pwr_req {
+				nvidia,pins = "core_pwr_req";
+				nvidia,function = "pwron";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			cpu_pwr_req {
+				nvidia,pins = "cpu_pwr_req";
+				nvidia,function = "cpu";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			pwr_int_n {
+				nvidia,pins = "pwr_int_n";
+				nvidia,function = "pmi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			reset_out_n {
+				nvidia,pins = "reset_out_n";
+				nvidia,function = "reset_out_n";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			clk3_out_pee0 {
+				nvidia,pins = "clk3_out_pee0";
+				nvidia,function = "extperiph3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gen1_i2c_scl_pc4 {
+				nvidia,pins = "gen1_i2c_scl_pc4",
+						"gen1_i2c_sda_pc5";
+				nvidia,function = "i2c1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+				nvidia,open-drain = <0>;
+			};
+			uart2_cts_n_pj5 {
+				nvidia,pins = "uart2_cts_n_pj5";
+				nvidia,function = "uartb";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			uart2_rts_n_pj6 {
+				nvidia,pins = "uart2_rts_n_pj6";
+				nvidia,function = "uartb";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			uart2_rxd_pc3 {
+				nvidia,pins = "uart2_rxd_pc3";
+				nvidia,function = "irda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			uart2_txd_pc2 {
+				nvidia,pins = "uart2_txd_pc2";
+				nvidia,function = "irda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			uart3_cts_n_pa1 {
+				nvidia,pins = "uart3_cts_n_pa1",
+						"uart3_rxd_pw7";
+				nvidia,function = "uartc";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			uart3_rts_n_pc0 {
+				nvidia,pins = "uart3_rts_n_pc0",
+						"uart3_txd_pw6";
+				nvidia,function = "uartc";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			owr {
+				nvidia,pins = "owr";
+				nvidia,function = "owr";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			hdmi_cec_pee3 {
+				nvidia,pins = "hdmi_cec_pee3";
+				nvidia,function = "cec";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+				nvidia,open-drain = <0>;
+			};
+			ddc_scl_pv4 {
+				nvidia,pins = "ddc_scl_pv4",
+						"ddc_sda_pv5";
+				nvidia,function = "i2c4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+				nvidia,rcv-sel = <1>;
+			};
+			spdif_in_pk6 {
+				nvidia,pins = "spdif_in_pk6";
+				nvidia,function = "usb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+			};
+			usb_vbus_en0_pn4 {
+				nvidia,pins = "usb_vbus_en0_pn4";
+				nvidia,function = "usb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+				nvidia,lock = <0>;
+				nvidia,open-drain = <1>;
+			};
+			gpio_x6_aud_px6 {
+				nvidia,pins = "gpio_x6_aud_px6";
+				nvidia,function = "spi6";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <1>;
+			};
+			gpio_x4_aud_px4 {
+				nvidia,pins = "gpio_x4_aud_px4",
+						"gpio_x7_aud_px7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gpio_x5_aud_px5 {
+				nvidia,pins = "gpio_x5_aud_px5";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gpio_w2_aud_pw2 {
+				nvidia,pins = "gpio_w2_aud_pw2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gpio_w3_aud_pw3 {
+				nvidia,pins = "gpio_w3_aud_pw3";
+				nvidia,function = "spi6";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gpio_x1_aud_px1 {
+				nvidia,pins = "gpio_x1_aud_px1";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gpio_x3_aud_px3 {
+				nvidia,pins = "gpio_x3_aud_px3";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			dap3_fs_pp0 {
+				nvidia,pins = "dap3_fs_pp0";
+				nvidia,function = "i2s2";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			dap3_dout_pp2 {
+				nvidia,pins = "dap3_dout_pp2";
+				nvidia,function = "i2s2";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			pv1 {
+				nvidia,pins = "pv1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			pbb3 {
+				nvidia,pins = "pbb3",
+						"pbb5",
+						"pbb6",
+						"pbb7";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			pcc1 {
+				nvidia,pins = "pcc1",
+						"pcc2";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gmi_ad0_pg0 {
+				nvidia,pins = "gmi_ad0_pg0",
+						"gmi_ad1_pg1";
+				nvidia,function = "gmi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gmi_ad10_ph2 {
+				nvidia,pins = "gmi_ad10_ph2",
+						"gmi_ad11_ph3",
+						"gmi_ad13_ph5",
+						"gmi_ad8_ph0",
+						"gmi_clk_pk1";
+				nvidia,function = "gmi";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			gmi_ad2_pg2 {
+				nvidia,pins = "gmi_ad2_pg2",
+						"gmi_ad3_pg3";
+				nvidia,function = "gmi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gmi_adv_n_pk0 {
+				nvidia,pins = "gmi_adv_n_pk0",
+						"gmi_cs0_n_pj0",
+						"gmi_cs2_n_pk3",
+						"gmi_cs4_n_pk2",
+						"gmi_cs7_n_pi6",
+						"gmi_dqs_p_pj3",
+						"gmi_iordy_pi5",
+						"gmi_wp_n_pc7";
+				nvidia,function = "gmi";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			gmi_cs3_n_pk4 {
+				nvidia,pins = "gmi_cs3_n_pk4";
+				nvidia,function = "gmi";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			clk2_req_pcc5 {
+				nvidia,pins = "clk2_req_pcc5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			kb_col3_pq3 {
+				nvidia,pins = "kb_col3_pq3",
+						"kb_col6_pq6",
+						"kb_col7_pq7";
+				nvidia,function = "kbc";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			kb_col5_pq5 {
+				nvidia,pins = "kb_col5_pq5";
+				nvidia,function = "kbc";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			kb_row3_pr3 {
+				nvidia,pins = "kb_row3_pr3",
+						"kb_row4_pr4",
+						"kb_row6_pr6",
+						"kb_row8_ps0";
+				nvidia,function = "kbc";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			clk3_req_pee1 {
+				nvidia,pins = "clk3_req_pee1";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			pu4 {
+				nvidia,pins = "pu4";
+				nvidia,function = "displayb";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <0>;
+			};
+			pu5 {
+				nvidia,pins = "pu5",
+						"pu6";
+				nvidia,function = "displayb";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			hdmi_int_pn7 {
+				nvidia,pins = "hdmi_int_pn7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+				nvidia,enable-input = <1>;
+			};
+			clk1_req_pee2 {
+				nvidia,pins = "clk1_req_pee2",
+						"usb_vbus_en1_pn5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+				nvidia,enable-input = <0>;
+			};
+
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <1>;
+				nvidia,schmitt = <0>;
+				nvidia,low-power-mode = <3>;
+				nvidia,pull-down-strength = <36>;
+				nvidia,pull-up-strength = <20>;
+				nvidia,slew-rate-rising = <2>;
+				nvidia,slew-rate-falling = <2>;
+			};
+			drive_sdio3 {
+				nvidia,pins = "drive_sdio3";
+				nvidia,high-speed-mode = <1>;
+				nvidia,schmitt = <0>;
+				nvidia,low-power-mode = <3>;
+				nvidia,pull-down-strength = <22>;
+				nvidia,pull-up-strength = <36>;
+				nvidia,slew-rate-rising = <0>;
+				nvidia,slew-rate-falling = <0>;
+			};
+			drive_gma {
+				nvidia,pins = "drive_gma";
+				nvidia,high-speed-mode = <1>;
+				nvidia,schmitt = <0>;
+				nvidia,low-power-mode = <3>;
+				nvidia,pull-down-strength = <2>;
+				nvidia,pull-up-strength = <1>;
+				nvidia,slew-rate-rising = <0>;
+				nvidia,slew-rate-falling = <0>;
+				nvidia,drive-type = <1>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ff95972487d5..36ab48bcbe63 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -339,6 +339,14 @@ config MACH_ROTH
        help
          Support for NVIDIA THOR development platform
 
+config MACH_TEGRATAB
+       bool "Tegratab board"
+       depends on ARCH_TEGRA_11x_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
+       help
+         Support for NVIDIA TEGRATAB development platform
+
 choice
        prompt "Tegra platform type"
        default TEGRA_SILICON_PLATFORM
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index ff5501499232..dff61b85da56 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -299,6 +299,17 @@ obj-${CONFIG_MACH_MACALLAN}             += board-macallan-kbc.o
 obj-${CONFIG_MACH_MACALLAN}             += board-macallan-sensors.o
 obj-${CONFIG_MACH_MACALLAN}             += panel-p-wuxga-10-1.o
 
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-memory.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-pinmux.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-power.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-powermon.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-sdhci.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-panel.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-kbc.o
+obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-sensors.o
+obj-${CONFIG_MACH_TEGRATAB}            += panel-p-wuxga-10-1.o
+
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto.o
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto-memory.o
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index dfcb4d747e63..14639f578eba 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -21,3 +21,4 @@ dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-dalmore.dtb
 dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-macallan.dtb
 dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-roth.dtb
 dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-pluto.dtb
+dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-tegratab.dtb
\ No newline at end of file
diff --git a/arch/arm/mach-tegra/board-tegratab-kbc.c b/arch/arm/mach-tegra/board-tegratab-kbc.c
new file mode 100644
index 000000000000..4528f6477373
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-kbc.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <mach/io.h>
+#include <linux/io.h>
+#include <mach/iomap.h>
+#include <mach/kbc.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/mfd/palmas.h>
+#include "wakeups-t11x.h"
+
+#include "tegra-board-id.h"
+#include "board.h"
+#include "board-tegratab.h"
+#include "devices.h"
+
+#define GPIO_KEY(_id, _gpio, _iswake)           \
+	{                                       \
+		.code = _id,                    \
+		.gpio = TEGRA_GPIO_##_gpio,     \
+		.active_low = 1,                \
+		.desc = #_id,                   \
+		.type = EV_KEY,                 \
+		.wakeup = _iswake,              \
+		.debounce_interval = 10,        \
+	}
+
+static struct gpio_keys_button tegratab_e1569_keys[] = {
+	[0] = GPIO_KEY(KEY_POWER, PQ0, 1),
+	[1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
+	[2] = GPIO_KEY(KEY_VOLUMEDOWN, PR1, 0),
+};
+
+static int tegratab_wakeup_key(void)
+{
+	int wakeup_key;
+	u64 status = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_WAKE_STATUS)
+		| (u64)readl(IO_ADDRESS(TEGRA_PMC_BASE)
+		+ PMC_WAKE2_STATUS) << 32;
+	if (status & ((u64)1 << TEGRA_WAKE_GPIO_PQ0))
+		wakeup_key = KEY_POWER;
+	else if (status & ((u64)1 << TEGRA_WAKE_GPIO_PS0))
+		wakeup_key = SW_LID;
+	else
+		wakeup_key = KEY_RESERVED;
+
+	return wakeup_key;
+}
+
+static struct gpio_keys_platform_data tegratab_e1569_keys_pdata = {
+	.buttons	= tegratab_e1569_keys,
+	.nbuttons	= ARRAY_SIZE(tegratab_e1569_keys),
+	.wakeup_key	= tegratab_wakeup_key,
+};
+
+static struct platform_device tegratab_e1569_keys_device = {
+	.name	= "gpio-keys",
+	.id	= 0,
+	.dev	= {
+		.platform_data  = &tegratab_e1569_keys_pdata,
+	},
+};
+
+int __init tegratab_kbc_init(void)
+{
+	platform_device_register(&tegratab_e1569_keys_device);
+
+	return 0;
+}
+
diff --git a/arch/arm/mach-tegra/board-tegratab-memory.c b/arch/arm/mach-tegra/board-tegratab-memory.c
new file mode 100644
index 000000000000..d50cde5c4688
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-memory.c
@@ -0,0 +1,2205 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_data/tegra_emc.h>
+
+#include "board.h"
+#include "board-tegratab.h"
+
+#include "tegra-board-id.h"
+#include "tegra11_emc.h"
+#include "fuse.h"
+#include "devices.h"
+
+static struct tegra11_emc_table e1569_mt41k128m16_125_table[] = {
+	{
+		0x41,       /* Rev 4.0.3 */
+		12750,      /* SDRAM frequency */
+		900,        /* min voltage */
+		"pll_p",    /* clock source id */
+		0x4000003e, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000000, /* EMC_RC */
+			0x00000003, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000000, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000006, /* EMC_IBDLY */
+			0x00010000, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000d, /* EMC_RDV_MASK */
+			0x00000060, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000005, /* EMC_TXSR */
+			0x00000005, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000001, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000064, /* EMC_TREFBW */
+			0x00000005, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000aa88, /* EMC_FBIO_CFG5 */
+			0x002c00a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03035504, /* EMC_XM2VTTGENPADCTRL */
+			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000042, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x40040001, /* MC_EMEM_ARB_CFG */
+			0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x77e30303, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x7320000e, /* EMC_CFG */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		57820,      /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		20400,      /* SDRAM frequency */
+		900,        /* min voltage */
+		"pll_p",    /* clock source id */
+		0x40000026, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000000, /* EMC_RC */
+			0x00000003, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000000, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000006, /* EMC_IBDLY */
+			0x00010000, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000d, /* EMC_RDV_MASK */
+			0x0000009a, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000005, /* EMC_TXSR */
+			0x00000006, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000001, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x000000a0, /* EMC_TREFBW */
+			0x00000005, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000aa88, /* EMC_FBIO_CFG5 */
+			0x002c00a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03035504, /* EMC_XM2VTTGENPADCTRL */
+			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000042, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x40020001, /* MC_EMEM_ARB_CFG */
+			0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x75430303, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000014, /* MC_PTSA_GRANT_DECREMENT */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x7320000e, /* EMC_CFG */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		35610,      /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		40800,      /* SDRAM frequency */
+		900,        /* min voltage */
+		"pll_p",    /* clock source id */
+		0x40000012, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000001, /* EMC_RC */
+			0x00000006, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000001, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000006, /* EMC_IBDLY */
+			0x00010000, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000d, /* EMC_RDV_MASK */
+			0x00000134, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000007, /* EMC_TXSR */
+			0x0000000c, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000002, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x0000013f, /* EMC_TREFBW */
+			0x00000005, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000aa88, /* EMC_FBIO_CFG5 */
+			0x002c00a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03035504, /* EMC_XM2VTTGENPADCTRL */
+			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000042, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0xa0000001, /* MC_EMEM_ARB_CFG */
+			0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x73630303, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
+			0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x7320000e, /* EMC_CFG */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		20850,      /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		68000,      /* SDRAM frequency */
+		900,        /* min voltage */
+		"pll_p",    /* clock source id */
+		0x4000000a, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000003, /* EMC_RC */
+			0x0000000a, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000002, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000006, /* EMC_IBDLY */
+			0x00010000, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000d, /* EMC_RDV_MASK */
+			0x00000202, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000008, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x0000000c, /* EMC_TXSR */
+			0x00000013, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000003, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000213, /* EMC_TREFBW */
+			0x00000005, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000aa88, /* EMC_FBIO_CFG5 */
+			0x002c00a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03035504, /* EMC_XM2VTTGENPADCTRL */
+			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000042, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x72c30403, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000046, /* MC_PTSA_GRANT_DECREMENT */
+			0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x7320000e, /* EMC_CFG */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		10720,      /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		102000,     /* SDRAM frequency */
+		900,        /* min voltage */
+		"pll_p",    /* clock source id */
+		0x40000006, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000004, /* EMC_RC */
+			0x00000010, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000003, /* EMC_RAS */
+			0x00000001, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000001, /* EMC_RD_RCD */
+			0x00000001, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000006, /* EMC_IBDLY */
+			0x00010000, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000d, /* EMC_RDV_MASK */
+			0x00000303, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000d, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000012, /* EMC_TXSR */
+			0x0000001c, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000005, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x0000031c, /* EMC_TREFBW */
+			0x00000005, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000aa88, /* EMC_FBIO_CFG5 */
+			0x002c00a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03035504, /* EMC_XM2VTTGENPADCTRL */
+			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000042, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x08000001, /* MC_EMEM_ARB_CFG */
+			0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+			0x72830504, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000068, /* MC_PTSA_GRANT_DECREMENT */
+			0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x7320000e, /* EMC_CFG */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		6890,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		204000,     /* SDRAM frequency */
+		900,        /* min voltage */
+		"pll_p",    /* clock source id */
+		0x40000002, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000009, /* EMC_RC */
+			0x00000020, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000007, /* EMC_RAS */
+			0x00000002, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000002, /* EMC_RD_RCD */
+			0x00000002, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000006, /* EMC_IBDLY */
+			0x00010000, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000d, /* EMC_RDV_MASK */
+			0x00000607, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000001d, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000023, /* EMC_TXSR */
+			0x00000038, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000009, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000638, /* EMC_TREFBW */
+			0x00000006, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000aa88, /* EMC_FBIO_CFG5 */
+			0x000000a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x01000003, /* MC_EMEM_ARB_CFG */
+			0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
+			0x72440a06, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000007, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000808, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000007, /* EMC_QUSE */
+			0x00000004, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+			0x00000009, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+			0x20820800, /* EMC_XM2DQSPADCTRL3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000808, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+			0x00048000, /* EMC_DLL_XFORM_DQ1 */
+			0x00048000, /* EMC_DLL_XFORM_DQ2 */
+			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
+			0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x7320000e, /* EMC_CFG */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		3420,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		312000,     /* SDRAM frequency */
+		1000,       /* min voltage */
+		"pll_c",    /* clock source id */
+		0x24000002, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x0000000e, /* EMC_RC */
+			0x00000030, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000009, /* EMC_RAS */
+			0x00000003, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x00000008, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x00000009, /* EMC_W2P */
+			0x00000003, /* EMC_RD_RCD */
+			0x00000003, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000004, /* EMC_WDV */
+			0x00000004, /* EMC_WDV_MASK */
+			0x00000007, /* EMC_IBDLY */
+			0x00080006, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000d, /* EMC_RDV_MASK */
+			0x00000945, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000001, /* EMC_PDEX2WR */
+			0x00000008, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000002e, /* EMC_AR2PDEN */
+			0x0000000e, /* EMC_RW2PDEN */
+			0x00000036, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x0000000d, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000986, /* EMC_TREFBW */
+			0x00000006, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000ba88, /* EMC_FBIO_CFG5 */
+			0x002c00a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00030000, /* EMC_DLL_XFORM_DQS4 */
+			0x00030000, /* EMC_DLL_XFORM_DQS5 */
+			0x00030000, /* EMC_DLL_XFORM_DQS6 */
+			0x00030000, /* EMC_DLL_XFORM_DQS7 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0001013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03035504, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0190000c, /* EMC_MRS_WAIT_CNT */
+			0x0190000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x0b000004, /* MC_EMEM_ARB_CFG */
+			0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000007, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
+			0x76e50f08, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x00030000, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000b, /* EMC_QSAFE */
+			0x00028000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x00030000, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00024000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00024000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00024000, /* EMC_DLL_XFORM_ADDR2 */
+			0x00030000, /* EMC_DLL_XFORM_DQS1 */
+			0x00030000, /* EMC_DLL_XFORM_DQS2 */
+			0x00030000, /* EMC_DLL_XFORM_DQS3 */
+			0x00030000, /* EMC_DLL_XFORM_DQ1 */
+			0x00030000, /* EMC_DLL_XFORM_DQ2 */
+			0x00030000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x00030000, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000b, /* EMC_QSAFE */
+			0x00028000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000d, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x00030000, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00024000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00024000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00024000, /* EMC_DLL_XFORM_ADDR2 */
+			0x00030000, /* EMC_DLL_XFORM_DQS1 */
+			0x00030000, /* EMC_DLL_XFORM_DQS2 */
+			0x00030000, /* EMC_DLL_XFORM_DQS3 */
+			0x00030000, /* EMC_DLL_XFORM_DQ1 */
+			0x00030000, /* EMC_DLL_XFORM_DQ2 */
+			0x00030000, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00028000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000140, /* MC_PTSA_GRANT_DECREMENT */
+			0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x5320000e, /* EMC_CFG */
+		0x80000321, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200000, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		2680,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		408000,     /* SDRAM frequency */
+		1000,       /* min voltage */
+		"pll_p",    /* clock source id */
+		0x40000000, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000012, /* EMC_RC */
+			0x00000040, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x0000000d, /* EMC_RAS */
+			0x00000004, /* EMC_RP */
+			0x00000005, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000c, /* EMC_W2P */
+			0x00000004, /* EMC_RD_RCD */
+			0x00000004, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000004, /* EMC_WDV */
+			0x00000004, /* EMC_WDV_MASK */
+			0x00000007, /* EMC_IBDLY */
+			0x00080006, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000004, /* EMC_QRST */
+			0x0000000e, /* EMC_RDV_MASK */
+			0x00000c2f, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000001, /* EMC_PDEX2WR */
+			0x00000008, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000003d, /* EMC_AR2PDEN */
+			0x00000011, /* EMC_RW2PDEN */
+			0x00000046, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000011, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000c70, /* EMC_TREFBW */
+			0x00000006, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000ba88, /* EMC_FBIO_CFG5 */
+			0x002c0080, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00018000, /* EMC_DLL_XFORM_DQS4 */
+			0x00018000, /* EMC_DLL_XFORM_DQS5 */
+			0x00018000, /* EMC_DLL_XFORM_DQS6 */
+			0x00018000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0001013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03035504, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0181000c, /* EMC_MRS_WAIT_CNT */
+			0x0181000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x02000006, /* MC_EMEM_ARB_CFG */
+			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
+			0x7547130b, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x00018000, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000e, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x00020001, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000005, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000005, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000005, /* EMC_DLL_XFORM_ADDR2 */
+			0x00018000, /* EMC_DLL_XFORM_DQS1 */
+			0x00018000, /* EMC_DLL_XFORM_DQS2 */
+			0x00018000, /* EMC_DLL_XFORM_DQS3 */
+			0x00020001, /* EMC_DLL_XFORM_DQ1 */
+			0x00020001, /* EMC_DLL_XFORM_DQ2 */
+			0x00020001, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x00018000, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000000e, /* EMC_RDV */
+			0x00208208, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x00020001, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000005, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000005, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000005, /* EMC_DLL_XFORM_ADDR2 */
+			0x00018000, /* EMC_DLL_XFORM_DQS1 */
+			0x00018000, /* EMC_DLL_XFORM_DQS2 */
+			0x00018000, /* EMC_DLL_XFORM_DQS3 */
+			0x00020001, /* EMC_DLL_XFORM_DQ1 */
+			0x00020001, /* EMC_DLL_XFORM_DQ2 */
+			0x00020001, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
+			0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x53200006, /* EMC_CFG */
+		0x80000731, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		1750,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		528000,     /* SDRAM frequency */
+		1100,       /* min voltage */
+		"pll_m",    /* clock source id */
+		0x80000000, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000018, /* EMC_RC */
+			0x00000053, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000010, /* EMC_RAS */
+			0x00000006, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000d, /* EMC_W2P */
+			0x00000006, /* EMC_RD_RCD */
+			0x00000006, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000009, /* EMC_IBDLY */
+			0x00090007, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000007, /* EMC_QRST */
+			0x00000010, /* EMC_RDV_MASK */
+			0x00000fd8, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000003f6, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x0000000b, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000050, /* EMC_AR2PDEN */
+			0x00000012, /* EMC_RW2PDEN */
+			0x0000005a, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000016, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000005, /* EMC_TCLKSTABLE */
+			0x00000006, /* EMC_TCLKSTOP */
+			0x00001019, /* EMC_TREFBW */
+			0x00000008, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000ba88, /* EMC_FBIO_CFG5 */
+			0xf0120091, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x07077504, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x016e000c, /* EMC_MRS_WAIT_CNT */
+			0x016e000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80002066, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x0f000007, /* MC_EMEM_ARB_CFG */
+			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
+			0x7428180e, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000009, /* EMC_QUSE */
+			0x00000007, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000010, /* EMC_RDV */
+			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000909, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000009, /* EMC_QUSE */
+			0x00000007, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000010, /* EMC_RDV */
+			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000909, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x0000010e, /* MC_PTSA_GRANT_DECREMENT */
+			0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x73100004, /* EMC_CFG */
+		0x80000941, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		1440,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		624000,     /* SDRAM frequency */
+		1100,       /* min voltage */
+		"pll_c",    /* clock source id */
+		0x24000000, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x0000001d, /* EMC_RC */
+			0x00000062, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000014, /* EMC_RAS */
+			0x00000007, /* EMC_RP */
+			0x00000007, /* EMC_R2W */
+			0x0000000b, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x00000010, /* EMC_W2P */
+			0x00000007, /* EMC_RD_RCD */
+			0x00000007, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x0000000a, /* EMC_IBDLY */
+			0x000c000a, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000007, /* EMC_QRST */
+			0x00000012, /* EMC_RDV_MASK */
+			0x000012c4, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x0000000d, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000005e, /* EMC_AR2PDEN */
+			0x00000015, /* EMC_RW2PDEN */
+			0x0000006b, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000005, /* EMC_TCKE */
+			0x00000005, /* EMC_TCKESR */
+			0x00000005, /* EMC_TPD */
+			0x00000019, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000006, /* EMC_TCLKSTABLE */
+			0x00000007, /* EMC_TCLKSTOP */
+			0x00001305, /* EMC_TREFBW */
+			0x00000009, /* EMC_QUSE_EXTRA */
+			0x00000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000ba88, /* EMC_FBIO_CFG5 */
+			0xf00d0191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x007f800b, /* EMC_DLL_XFORM_DQS4 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS5 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS6 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x07077504, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0160000c, /* EMC_MRS_WAIT_CNT */
+			0x0160000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x06000009, /* MC_EMEM_ARB_CFG */
+			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
+			0x07050202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
+			0x736a1d10, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x0000000a, /* EMC_QUSE */
+			0x00000008, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x007f800b, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000012, /* EMC_RDV */
+			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x00000009, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000909, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS1 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS2 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS3 */
+			0x00000009, /* EMC_DLL_XFORM_DQ1 */
+			0x00000009, /* EMC_DLL_XFORM_DQ2 */
+			0x00000009, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x0000000a, /* EMC_QUSE */
+			0x00000008, /* EMC_EINPUT */
+			0x00000004, /* EMC_EINPUT_DURATION */
+			0x007f800b, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000012, /* EMC_RDV */
+			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x00000009, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000909, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS1 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS2 */
+			0x007f800b, /* EMC_DLL_XFORM_DQS3 */
+			0x00000009, /* EMC_DLL_XFORM_DQ1 */
+			0x00000009, /* EMC_DLL_XFORM_DQ2 */
+			0x00000009, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
+			0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x53200000, /* EMC_CFG */
+		0x80000b61, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200010, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		1440,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x41,       /* Rev 4.0.3 */
+		792000,     /* SDRAM frequency */
+		1100,       /* min voltage */
+		"pll_m",    /* clock source id */
+		0x80000000, /* CLK_SOURCE_EMC */
+		99,         /* number of burst_regs */
+		30,         /* number of trim_regs (each channel) */
+		11,         /* number of up_down_regs */
+		{
+			0x00000024, /* EMC_RC */
+			0x0000007d, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000019, /* EMC_RAS */
+			0x0000000a, /* EMC_RP */
+			0x00000009, /* EMC_R2W */
+			0x0000000d, /* EMC_W2R */
+			0x00000004, /* EMC_R2P */
+			0x00000013, /* EMC_W2P */
+			0x0000000a, /* EMC_RD_RCD */
+			0x0000000a, /* EMC_WR_RCD */
+			0x00000004, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000006, /* EMC_WDV */
+			0x00000006, /* EMC_WDV_MASK */
+			0x0000000b, /* EMC_IBDLY */
+			0x000d000a, /* EMC_PUTERM_EXTRA */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000008, /* EMC_QRST */
+			0x00000014, /* EMC_RDV_MASK */
+			0x000017e4, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000003, /* EMC_PDEX2WR */
+			0x00000012, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000077, /* EMC_AR2PDEN */
+			0x00000018, /* EMC_RW2PDEN */
+			0x00000087, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000005, /* EMC_TCKE */
+			0x00000005, /* EMC_TCKESR */
+			0x00000005, /* EMC_TPD */
+			0x00000020, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000007, /* EMC_TCLKSTABLE */
+			0x00000008, /* EMC_TCLKSTOP */
+			0x00001825, /* EMC_TREFBW */
+			0x0000000a, /* EMC_QUSE_EXTRA */
+			0x80000020, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x0000ba88, /* EMC_FBIO_CFG5 */
+			0xf0070191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00000008, /* EMC_DLL_XFORM_DQS4 */
+			0x00000008, /* EMC_DLL_XFORM_DQS5 */
+			0x00000008, /* EMC_DLL_XFORM_DQS6 */
+			0x00000008, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x001112a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x81f1f508, /* EMC_XM2COMPPADCTRL */
+			0x07076604, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x02000000, /* EMC_FBIO_SPARE */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0147000c, /* EMC_MRS_WAIT_CNT */
+			0x0147000c, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80003018, /* EMC_DYN_SELF_REF_CONTROL */
+			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+			0x0e00000b, /* MC_EMEM_ARB_CFG */
+			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08060202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
+			0x72cc2414, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x0000000b, /* EMC_QUSE */
+			0x00000008, /* EMC_EINPUT */
+			0x00000006, /* EMC_EINPUT_DURATION */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000d, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000014, /* EMC_RDV */
+			0x00249249, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+			0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS3 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ1 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ2 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x0000000b, /* EMC_QUSE */
+			0x00000008, /* EMC_EINPUT */
+			0x00000006, /* EMC_EINPUT_DURATION */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000d, /* EMC_QSAFE */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000014, /* EMC_RDV */
+			0x00249249, /* EMC_XM2DQSPADCTRL4 */
+			0x10410400, /* EMC_XM2DQSPADCTRL3 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+			0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS3 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ1 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ2 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+		},
+		{
+			0x00000196, /* MC_PTSA_GRANT_DECREMENT */
+			0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
+			0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
+			0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
+			0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+			0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
+			0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
+			0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+			0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
+			0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+			0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x73000000, /* EMC_CFG */
+		0x80000d71, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200218, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		1200,       /* expected dvfs latency (ns) */
+	},
+};
+
+static struct tegra11_emc_pdata e1569_mt41k128m16_125_pdata = {
+	.description = "e1569_mt41k128m16_125",
+	.tables = e1569_mt41k128m16_125_table,
+	.num_tables = ARRAY_SIZE(e1569_mt41k128m16_125_table),
+};
+
+static struct tegra11_emc_pdata *tegratab_get_emc_data(void)
+{
+	return &e1569_mt41k128m16_125_pdata;
+}
+
+int __init tegratab_emc_init(void)
+{
+	tegra_emc_device.dev.platform_data = tegratab_get_emc_data();
+	platform_device_register(&tegra_emc_device);
+	tegra11_emc_init();
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-tegratab-panel.c b/arch/arm/mach-tegra/board-tegratab-panel.c
new file mode 100644
index 000000000000..2d0d051f4079
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-panel.c
@@ -0,0 +1,518 @@
+/*
+ * arch/arm/mach-tegra/board-tegratab-panel.c
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/ioport.h>
+#include <linux/fb.h>
+#include <linux/nvmap.h>
+#include <linux/nvhost.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/tegra_pwm_bl.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pwm_backlight.h>
+
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+
+#include "board.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "board-panel.h"
+#include "common.h"
+#include "tegra11_host1x_devices.h"
+
+struct platform_device * __init tegratab_host1x_init(void)
+{
+	struct platform_device *pdev = NULL;
+
+#ifdef CONFIG_TEGRA_GRHOST
+	pdev = tegra11_register_host1x_devices();
+	if (!pdev) {
+		pr_err("host1x devices registration failed\n");
+		return NULL;
+	}
+#endif
+	return pdev;
+}
+
+#ifdef CONFIG_TEGRA_DC
+
+/* HDMI Hotplug detection pin */
+#define tegratab_hdmi_hpd	TEGRA_GPIO_PN7
+
+static struct regulator *tegratab_hdmi_reg;
+static struct regulator *tegratab_hdmi_pll;
+static struct regulator *tegratab_hdmi_vddio;
+
+static struct resource tegratab_disp1_resources[] = {
+	{
+		.name	= "irq",
+		.start	= INT_DISPLAY_GENERAL,
+		.end	= INT_DISPLAY_GENERAL,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "regs",
+		.start	= TEGRA_DISPLAY_BASE,
+		.end	= TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "fbmem",
+		.start	= 0, /* Filled in by tegratab_panel_init() */
+		.end	= 0, /* Filled in by tegratab_panel_init() */
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "ganged_dsia_regs",
+		.start	= 0, /* Filled in the panel file by init_resources() */
+		.end	= 0, /* Filled in the panel file by init_resources() */
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "ganged_dsib_regs",
+		.start	= 0, /* Filled in the panel file by init_resources() */
+		.end	= 0, /* Filled in the panel file by init_resources() */
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "dsi_regs",
+		.start	= 0, /* Filled in the panel file by init_resources() */
+		.end	= 0, /* Filled in the panel file by init_resources() */
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "mipi_cal",
+		.start	= TEGRA_MIPI_CAL_BASE,
+		.end	= TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource tegratab_disp2_resources[] = {
+	{
+		.name	= "irq",
+		.start	= INT_DISPLAY_B_GENERAL,
+		.end	= INT_DISPLAY_B_GENERAL,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "regs",
+		.start	= TEGRA_DISPLAY2_BASE,
+		.end	= TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "fbmem",
+		.start	= 0, /* Filled in by tegratab_panel_init() */
+		.end	= 0, /* Filled in by tegratab_panel_init() */
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "hdmi_regs",
+		.start	= TEGRA_HDMI_BASE,
+		.end	= TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+
+static struct tegra_dc_sd_settings sd_settings;
+
+static struct tegra_dc_out tegratab_disp1_out = {
+	.type		= TEGRA_DC_OUT_DSI,
+	/*
+	 * In the early bring-up stage, we will not enable
+	 * PRISM.
+	 * TODO. enable PRISM later.
+	 */
+	.sd_settings	= NULL,
+	/*
+	 * .sd_settings	= &sd_settings,
+	 */
+};
+
+static int tegratab_hdmi_enable(struct device *dev)
+{
+	int ret;
+	if (!tegratab_hdmi_reg) {
+		tegratab_hdmi_reg = regulator_get(dev, "avdd_hdmi");
+		if (IS_ERR_OR_NULL(tegratab_hdmi_reg)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+			tegratab_hdmi_reg = NULL;
+			return PTR_ERR(tegratab_hdmi_reg);
+		}
+	}
+	ret = regulator_enable(tegratab_hdmi_reg);
+	if (ret < 0) {
+		pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
+		return ret;
+	}
+	if (!tegratab_hdmi_pll) {
+		tegratab_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
+		if (IS_ERR_OR_NULL(tegratab_hdmi_pll)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+			tegratab_hdmi_pll = NULL;
+			regulator_put(tegratab_hdmi_reg);
+			tegratab_hdmi_reg = NULL;
+			return PTR_ERR(tegratab_hdmi_pll);
+		}
+	}
+	ret = regulator_enable(tegratab_hdmi_pll);
+	if (ret < 0) {
+		pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
+		return ret;
+	}
+	return 0;
+}
+
+static int tegratab_hdmi_disable(void)
+{
+	if (tegratab_hdmi_reg) {
+		regulator_disable(tegratab_hdmi_reg);
+		regulator_put(tegratab_hdmi_reg);
+		tegratab_hdmi_reg = NULL;
+	}
+
+	if (tegratab_hdmi_pll) {
+		regulator_disable(tegratab_hdmi_pll);
+		regulator_put(tegratab_hdmi_pll);
+		tegratab_hdmi_pll = NULL;
+	}
+
+	return 0;
+}
+
+static int tegratab_hdmi_postsuspend(void)
+{
+	if (tegratab_hdmi_vddio) {
+		regulator_disable(tegratab_hdmi_vddio);
+		regulator_put(tegratab_hdmi_vddio);
+		tegratab_hdmi_vddio = NULL;
+	}
+	return 0;
+}
+
+static int tegratab_hdmi_hotplug_init(struct device *dev)
+{
+	if (!tegratab_hdmi_vddio) {
+		tegratab_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
+		if (WARN_ON(IS_ERR(tegratab_hdmi_vddio))) {
+			pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
+				__func__, PTR_ERR(tegratab_hdmi_vddio));
+				tegratab_hdmi_vddio = NULL;
+		} else {
+			regulator_enable(tegratab_hdmi_vddio);
+			mdelay(5);
+		}
+	}
+
+	return 0;
+}
+
+static struct tegra_dc_out tegratab_disp2_out = {
+	.type		= TEGRA_DC_OUT_HDMI,
+	.flags		= TEGRA_DC_OUT_HOTPLUG_HIGH,
+	.parent_clk	= "pll_d2_out0",
+
+	.dcc_bus	= 3,
+	.hotplug_gpio	= tegratab_hdmi_hpd,
+
+	.max_pixclock	= KHZ2PICOS(297000),
+
+	.align		= TEGRA_DC_ALIGN_MSB,
+	.order		= TEGRA_DC_ORDER_RED_BLUE,
+
+	.enable		= tegratab_hdmi_enable,
+	.disable	= tegratab_hdmi_disable,
+	.postsuspend	= tegratab_hdmi_postsuspend,
+	.hotplug_init	= tegratab_hdmi_hotplug_init,
+};
+
+static struct tegra_fb_data tegratab_disp1_fb_data = {
+	.win		= 0,
+	.bits_per_pixel = 32,
+	.flags		= TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data tegratab_disp1_pdata = {
+	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.default_out	= &tegratab_disp1_out,
+	.fb		= &tegratab_disp1_fb_data,
+	.emc_clk_rate	= 204000000,
+	/*
+	 * In early panel bring-up stage, we will not
+	 * enable CMU. Check if CONFIG_TEGRA_DC_CMU is
+	 * removed in early bring-up stage as well.
+	 * TODO...enable CMU later.
+	 */
+#ifdef CONFIG_TEGRA_DC_CMU
+	.cmu_enable	= 0,
+	/*.cmu_enable	= 1,*/
+#endif
+};
+
+static struct tegra_fb_data tegratab_disp2_fb_data = {
+	.win		= 0,
+	.xres		= 1024,
+	.yres		= 600,
+	.bits_per_pixel = 32,
+	.flags		= TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data tegratab_disp2_pdata = {
+	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.default_out	= &tegratab_disp2_out,
+	.fb		= &tegratab_disp2_fb_data,
+	.emc_clk_rate	= 300000000,
+};
+
+static struct platform_device tegratab_disp2_device = {
+	.name		= "tegradc",
+	.id		= 1,
+	.resource	= tegratab_disp2_resources,
+	.num_resources	= ARRAY_SIZE(tegratab_disp2_resources),
+	.dev = {
+		.platform_data = &tegratab_disp2_pdata,
+	},
+};
+
+static struct platform_device tegratab_disp1_device = {
+	.name		= "tegradc",
+	.id		= 0,
+	.resource	= tegratab_disp1_resources,
+	.num_resources	= ARRAY_SIZE(tegratab_disp1_resources),
+	.dev = {
+		.platform_data = &tegratab_disp1_pdata,
+	},
+};
+
+static struct nvmap_platform_carveout tegratab_carveouts[] = {
+	[0] = {
+		.name		= "iram",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_IRAM,
+		.base		= TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
+		.size		= TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
+		.buddy_size	= 0, /* no buddy allocation for IRAM */
+	},
+	[1] = {
+		.name		= "generic-0",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_GENERIC,
+		.base		= 0, /* Filled in by tegratab_panel_init() */
+		.size		= 0, /* Filled in by tegratab_panel_init() */
+		.buddy_size	= SZ_32K,
+	},
+	[2] = {
+		.name		= "vpr",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_VPR,
+		.base		= 0, /* Filled in by tegratab_panel_init() */
+		.size		= 0, /* Filled in by tegratab_panel_init() */
+		.buddy_size	= SZ_32K,
+	},
+};
+
+static struct nvmap_platform_data tegratab_nvmap_data = {
+	.carveouts	= tegratab_carveouts,
+	.nr_carveouts	= ARRAY_SIZE(tegratab_carveouts),
+};
+static struct platform_device tegratab_nvmap_device __initdata = {
+	.name	= "tegra-nvmap",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &tegratab_nvmap_data,
+	},
+};
+
+static struct tegra_dc_sd_settings tegratab_sd_settings = {
+	/*
+	 * In early panel bring-up stage,
+	 * we will disable PRISM.
+	 * TODO. enable PRISM later.
+	 */
+	.enable = 0,
+	/*.enable = 1, */ /* enabled by default. */
+	.use_auto_pwm = false,
+	.hw_update_delay = 0,
+	.bin_width = -1,
+	.aggressiveness = 5,
+	.use_vid_luma = false,
+	.phase_in_adjustments = 0,
+	.k_limit_enable = true,
+	.k_limit = 200,
+	.sd_window_enable = false,
+	.soft_clipping_enable = true,
+	/* Low soft clipping threshold to compensate for aggressive k_limit */
+	.soft_clipping_threshold = 128,
+	.smooth_k_enable = false,
+	.smooth_k_incr = 64,
+	/* Default video coefficients */
+	.coeff = {5, 9, 2},
+	.fc = {0, 0},
+	/* Immediate backlight changes */
+	.blp = {1024, 255},
+	/* Gammas: R: 2.2 G: 2.2 B: 2.2 */
+	/* Default BL TF */
+	.bltf = {
+			{
+				{57, 65, 73, 82},
+				{92, 103, 114, 125},
+				{138, 150, 164, 178},
+				{193, 208, 224, 241},
+			},
+		},
+	/* Default LUT */
+	.lut = {
+			{
+				{255, 255, 255},
+				{199, 199, 199},
+				{153, 153, 153},
+				{116, 116, 116},
+				{85, 85, 85},
+				{59, 59, 59},
+				{36, 36, 36},
+				{17, 17, 17},
+				{0, 0, 0},
+			},
+		},
+	.sd_brightness = &sd_brightness,
+	.use_vpulse2 = true,
+};
+
+static void tegratab_panel_select(void)
+{
+	struct tegra_panel *panel = NULL;
+	struct board_info board;
+
+	tegra_get_display_board_info(&board);
+
+	switch (board.board_id) {
+	default:
+		panel = &dsi_p_wuxga_10_1;
+		break;
+	}
+	if (panel) {
+		if (panel->init_sd_settings)
+			panel->init_sd_settings(&sd_settings);
+
+		if (panel->init_dc_out)
+			panel->init_dc_out(&tegratab_disp1_out);
+
+		if (panel->init_fb_data)
+			panel->init_fb_data(&tegratab_disp1_fb_data);
+
+		if (panel->init_cmu_data)
+			panel->init_cmu_data(&tegratab_disp1_pdata);
+
+		if (panel->set_disp_device)
+			panel->set_disp_device(&tegratab_disp1_device);
+
+		if (panel->init_resources)
+			panel->init_resources(tegratab_disp1_resources,
+				ARRAY_SIZE(tegratab_disp1_resources));
+
+		if (panel->register_bl_dev)
+			panel->register_bl_dev();
+
+		if (panel->register_i2c_bridge)
+			panel->register_i2c_bridge();
+	}
+
+}
+int __init tegratab_panel_init(void)
+{
+	int err = 0;
+	struct resource __maybe_unused *res;
+	struct platform_device *phost1x;
+
+	sd_settings = tegratab_sd_settings;
+
+	tegratab_panel_select();
+
+#ifdef CONFIG_TEGRA_NVMAP
+	tegratab_carveouts[1].base = tegra_carveout_start;
+	tegratab_carveouts[1].size = tegra_carveout_size;
+	tegratab_carveouts[2].base = tegra_vpr_start;
+	tegratab_carveouts[2].size = tegra_vpr_size;
+
+	err = platform_device_register(&tegratab_nvmap_device);
+	if (err) {
+		pr_err("nvmap device registration failed\n");
+		return err;
+	}
+#endif
+
+	phost1x = tegratab_host1x_init();
+	if (!phost1x) {
+		pr_err("host1x devices registration failed\n");
+		return -EINVAL;
+	}
+
+	gpio_request(tegratab_hdmi_hpd, "hdmi_hpd");
+	gpio_direction_input(tegratab_hdmi_hpd);
+
+	res = platform_get_resource_byname(&tegratab_disp1_device,
+					 IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb_start;
+	res->end = tegra_fb_start + tegra_fb_size - 1;
+
+	/* Copy the bootloader fb to the fb. */
+	__tegra_move_framebuffer(&tegratab_nvmap_device,
+		tegra_fb_start, tegra_bootloader_fb_start,
+			min(tegra_fb_size, tegra_bootloader_fb_size));
+
+	res = platform_get_resource_byname(&tegratab_disp2_device,
+		IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb2_start;
+	res->end = tegra_fb2_start + tegra_fb2_size - 1;
+
+	tegratab_disp1_device.dev.parent = &phost1x->dev;
+	err = platform_device_register(&tegratab_disp1_device);
+	if (err) {
+		pr_err("disp1 device registration failed\n");
+		return err;
+	}
+
+	tegratab_disp2_device.dev.parent = &phost1x->dev;
+	err = platform_device_register(&tegratab_disp2_device);
+	if (err) {
+		pr_err("disp2 device registration failed\n");
+		return err;
+	}
+
+#ifdef CONFIG_TEGRA_NVAVP
+	nvavp_device.dev.parent = &phost1x->dev;
+	err = platform_device_register(&nvavp_device);
+	if (err) {
+		pr_err("nvavp device registration failed\n");
+		return err;
+	}
+#endif
+	return err;
+}
+#else
+int __init tegratab_panel_init(void)
+{
+	if (tegratab_host1x_init())
+		return 0;
+	else
+		return -EINVAL;
+}
+#endif
diff --git a/arch/arm/mach-tegra/board-tegratab-pinmux-t11x.h b/arch/arm/mach-tegra/board-tegratab-pinmux-t11x.h
new file mode 100644
index 000000000000..ab8fa3de01a4
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-pinmux-t11x.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* DO NOT EDIT THIS FILE. THIS FILE IS GENERATED FROM TEGRATAB_PINMUX.XLSM */
+
+
+static __initdata struct tegra_pingroup_config tegratab_pinmux_common[] = {
+
+	/* EXTPERIPH1 pinmux */
+	DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2S0 pinmux */
+	DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2S1 pinmux */
+	DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* CLDVFS pinmux */
+	DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+	/* SPI1 pinmux */
+	DEFAULT_PINMUX(ULPI_CLK,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR,      SPI1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_NXT,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(ULPI_STP,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* VI_ALT3 pinmux */
+	VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* UARTD pinmux */
+	DEFAULT_PINMUX(GMI_A16,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_A17,       UARTD,       NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_A18,       UARTD,       NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_A19,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SPI4 pinmux */
+	DEFAULT_PINMUX(GMI_AD5,       SPI4,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6,       SPI4,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7,       SPI4,        PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_WR_N,      SPI4,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* PWM1 pinmux */
+	DEFAULT_PINMUX(GMI_AD9,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* SOC pinmux */
+	DEFAULT_PINMUX(GMI_CS1_N,     SOC,         PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_OE_N,      SOC,         PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(CLK_32K_OUT,   SOC,         PULL_UP,   NORMAL,   INPUT),
+
+	/* EXTPERIPH2 pinmux */
+	DEFAULT_PINMUX(CLK2_OUT,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,  PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3,   PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL4,       SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CD_N,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+
+	/* SDMMC4 pinmux */
+	DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+
+	/* UARTA pinmux */
+	DEFAULT_PINMUX(KB_ROW10,      UARTA,       PULL_DOWN, NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW9,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
+
+	DEFAULT_PINMUX(KB_ROW6,       KBC,         PULL_DOWN, NORMAL,   INPUT),
+
+	/* KBC pinmux */
+	DEFAULT_PINMUX(KB_ROW8,       KBC,         PULL_UP,   NORMAL,   INPUT),
+
+	/* I2CPWR pinmux */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* SYSCLK pinmux */
+	DEFAULT_PINMUX(SYS_CLK_REQ,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
+
+	/* RTCK pinmux */
+	DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLK pinmux */
+	DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    NORMAL,   INPUT),
+
+	/* PWRON pinmux */
+	DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CPU pinmux */
+	DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+	/* PMI pinmux */
+	DEFAULT_PINMUX(PWR_INT_N,     PMI,         PULL_UP,   NORMAL,   INPUT),
+
+	/* RESET_OUT_N pinmux */
+	DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+	/* EXTPERIPH3 pinmux */
+	DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2S3 pinmux */
+	DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* UARTB pinmux */
+	DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* IRDA pinmux */
+	DEFAULT_PINMUX(UART2_RXD,     IRDA,        PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(UART2_TXD,     IRDA,        NORMAL,    NORMAL,   OUTPUT),
+
+	/* UARTC pinmux */
+	DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,     UARTC,       PULL_UP,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CEC pinmux */
+	CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C4 pinmux */
+	DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+	DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+
+	/* USB pinmux */
+	DEFAULT_PINMUX(USB_VBUS_EN0,  USB,         NORMAL,    NORMAL,   OUTPUT),
+
+	/* GPIO pinmux */
+	GPIO_PINMUX(GPIO_X4_AUD, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_X5_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_X6_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_X7_AUD, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_W2_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_W3_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_X1_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_X3_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(DAP3_DIN, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(DAP3_DOUT, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(DAP3_FS, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(DAP3_SCLK, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PV0, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PV1, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(ULPI_DATA2, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(ULPI_DATA3, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(ULPI_DATA4, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PBB3, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PBB4, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PBB5, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PBB6, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PBB7, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PCC1, PULL_DOWN, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PCC2, PULL_DOWN, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD0, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD1, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD10, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD11, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD12, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD13, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD14, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD2, NORMAL, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD3, NORMAL, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_AD8, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_ADV_N, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_CLK, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_CS0_N, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_CS2_N, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_CS3_N, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_CS4_N, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_CS7_N, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_DQS_P, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_IORDY, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GMI_RST_N, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_WAIT, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GMI_WP_N, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(CLK2_REQ, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(SDMMC1_WP_N, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(KB_COL0, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_COL1, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_COL2, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_COL3, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(KB_COL5, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_COL6, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(KB_COL7, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(KB_ROW0, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_ROW1, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_ROW2, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_ROW3, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_ROW4, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(KB_ROW5, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(KB_ROW7, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(CLK3_REQ, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PU0, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PU1, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PU2, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PU3, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PU4, NORMAL, NORMAL, OUTPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PU5, PULL_UP, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(GPIO_PU6, NORMAL, NORMAL, INPUT, DISABLE),
+	GPIO_PINMUX(HDMI_INT, PULL_DOWN, NORMAL, INPUT, DEFAULT),
+	GPIO_PINMUX(SPDIF_IN, NORMAL, NORMAL, OUTPUT, DISABLE),
+};
+
+static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
+	UNUSED_PINMUX(CLK1_REQ),
+	UNUSED_PINMUX(ULPI_DATA0),
+	UNUSED_PINMUX(ULPI_DATA1),
+	UNUSED_PINMUX(ULPI_DATA5),
+	UNUSED_PINMUX(ULPI_DATA6),
+	UNUSED_PINMUX(ULPI_DATA7),
+	UNUSED_PINMUX(GMI_AD15),
+	UNUSED_PINMUX(GMI_AD4),
+	UNUSED_PINMUX(GMI_CS6_N),
+	UNUSED_PINMUX(OWR),
+	UNUSED_PINMUX(SPDIF_OUT),
+	UNUSED_PINMUX(USB_VBUS_EN1),
+};
+
+static struct gpio_init_pin_info init_gpio_mode_tegratab_common[] = {
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX4, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX5, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX6, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX7, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW2, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW3, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX1, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX3, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP1, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP2, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP0, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP3, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV0, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV1, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO3, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO4, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO5, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB3, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB4, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB5, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB6, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB7, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC1, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC2, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG0, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG1, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH2, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH3, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH4, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH5, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH6, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG2, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG3, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH0, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK0, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK1, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ0, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK3, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK4, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK2, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI6, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ3, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI5, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI4, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI7, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC7, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC5, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV3, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ0, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ1, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ2, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ3, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ5, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ6, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ7, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR0, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR1, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR2, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR3, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR4, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR5, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR7, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PEE1, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU0, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU1, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU2, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU3, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU4, false, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU5, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU6, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN7, true, 0),
+	GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK6, false, 0),
+};
diff --git a/arch/arm/mach-tegra/board-tegratab-pinmux.c b/arch/arm/mach-tegra/board-tegratab-pinmux.c
new file mode 100644
index 000000000000..5dce5f05ca94
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-pinmux.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <mach/pinmux.h>
+#include <mach/gpio-tegra.h>
+#include "board.h"
+#include "board-tegratab.h"
+#include "devices.h"
+#include "gpio-names.h"
+
+#include <mach/pinmux-t11.h>
+
+#define DEFAULT_DRIVE(_name)					\
+	{							\
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,	\
+		.hsm = TEGRA_HSM_DISABLE,			\
+		.schmitt = TEGRA_SCHMITT_ENABLE,		\
+		.drive = TEGRA_DRIVE_DIV_1,			\
+		.pull_down = TEGRA_PULL_31,			\
+		.pull_up = TEGRA_PULL_31,			\
+		.slew_rising = TEGRA_SLEW_SLOWEST,		\
+		.slew_falling = TEGRA_SLEW_SLOWEST,		\
+	}
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive,	\
+		_pullup_drive, _pulldn_slew, _pullup_slew)	\
+	{							\
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,	\
+		.hsm = TEGRA_HSM_##_hsm,			\
+		.schmitt = TEGRA_SCHMITT_##_schmitt,		\
+		.drive = TEGRA_DRIVE_##_drive,			\
+		.pull_down = TEGRA_PULL_##_pulldn_drive,	\
+		.pull_up = TEGRA_PULL_##_pullup_drive,		\
+		.slew_rising = TEGRA_SLEW_##_pulldn_slew,	\
+		.slew_falling = TEGRA_SLEW_##_pullup_slew,	\
+	}
+
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * drive_type - Drive type to be used depending on the resistors.
+ */
+
+#define SET_DRIVE_WITH_TYPE(_name, _hsm, _schmitt, _drive, _pulldn_drive,\
+		_pullup_drive, _pulldn_slew, _pullup_slew, _drive_type)	\
+	{								\
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,		\
+		.hsm = TEGRA_HSM_##_hsm,				\
+		.schmitt = TEGRA_SCHMITT_##_schmitt,			\
+		.drive = TEGRA_DRIVE_##_drive,				\
+		.pull_down = TEGRA_PULL_##_pulldn_drive,		\
+		.pull_up = TEGRA_PULL_##_pullup_drive,			\
+		.slew_rising = TEGRA_SLEW_##_pulldn_slew,		\
+		.slew_falling = TEGRA_SLEW_##_pullup_slew,		\
+		.drive_type = TEGRA_DRIVE_TYPE_##_drive_type,		\
+	}
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)	\
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_DEFAULT,	\
+		.od		= TEGRA_PIN_OD_DEFAULT,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.od		= TEGRA_PIN_OD_##_od,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define DDC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _rcv_sel) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.rcv_sel	= TEGRA_PIN_RCV_SEL_##_rcv_sel,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.od		= TEGRA_PIN_OD_DEFAULT,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define CEC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od)   \
+	{                                                               \
+		.pingroup   = TEGRA_PINGROUP_##_pingroup,                   \
+		.func       = TEGRA_MUX_##_mux,                             \
+		.pupd       = TEGRA_PUPD_##_pupd,                           \
+		.tristate   = TEGRA_TRI_##_tri,                             \
+		.io         = TEGRA_PIN_##_io,                              \
+		.lock       = TEGRA_PIN_LOCK_##_lock,                       \
+		.od         = TEGRA_PIN_OD_##_od,                           \
+		.ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,                   \
+	}
+
+#define GPIO_PINMUX(_pingroup, _pupd, _tri, _io, _od)   \
+	{                                                   \
+		.pingroup   = TEGRA_PINGROUP_##_pingroup,       \
+		.func       = TEGRA_MUX_SAFE,                   \
+		.pupd       = TEGRA_PUPD_##_pupd,               \
+		.tristate   = TEGRA_TRI_##_tri,                 \
+		.io         = TEGRA_PIN_##_io,                  \
+		.lock       = TEGRA_PIN_LOCK_DEFAULT,           \
+		.od         = TEGRA_PIN_OD_##_od,               \
+		.ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
+	}
+
+#define UNUSED_PINMUX(_pingroup)                    \
+	{                                               \
+		.pingroup   = TEGRA_PINGROUP_##_pingroup,   \
+		.func       = TEGRA_MUX_SAFE,               \
+		.pupd       = TEGRA_PUPD_PULL_DOWN,         \
+		.tristate   = TEGRA_TRI_TRISTATE,           \
+		.io         = TEGRA_PIN_OUTPUT,             \
+		.lock       = TEGRA_PIN_LOCK_DEFAULT,       \
+		.od         = TEGRA_PIN_OD_DEFAULT,         \
+		.ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,   \
+	}
+
+#define USB_PINMUX CEC_PINMUX
+
+#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value)	\
+	{					\
+		.gpio_nr	= _gpio,	\
+		.is_input	= _is_input,	\
+		.value		= _value,	\
+	}
+
+static __initdata struct tegra_drive_pingroup_config tegratab_drive_pinmux[] = {
+	/* DEFAULT_DRIVE(<pin_group>), */
+	/* SDMMC1 */
+	SET_DRIVE(SDIO1, ENABLE, DISABLE, DIV_1, 36, 20, SLOW, SLOW),
+
+	/* SDMMC3 */
+	SET_DRIVE(SDIO3, ENABLE, DISABLE, DIV_1, 22, 36, FASTEST, FASTEST),
+
+	/* SDMMC4 */
+	SET_DRIVE_WITH_TYPE(GMA, ENABLE, DISABLE, DIV_1, 2, 1, FASTEST,
+								FASTEST, 1),
+};
+
+#include "board-tegratab-pinmux-t11x.h"
+
+/* THIS IS FOR TESTING OR WORKAROUND PURPOSES. ANYTHING INSIDE THIS TABLE
+ * SHOULD BE PUSHED TO PINMUX SPREADSHEET FOR AUTOGEN OR FIXED
+ * */
+static __initdata struct tegra_pingroup_config manual_config_pinmux[] = {
+
+	/* ULPI SFIOs are not supposed to be supported.
+	 * This setting is only for Tegratab. */
+	DEFAULT_PINMUX(ULPI_DATA0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7,    ULPI,        NORMAL,    NORMAL,   INPUT),
+};
+
+static void __init tegratab_gpio_init_configure(void)
+{
+	int len;
+	int i;
+	struct gpio_init_pin_info *pins_info;
+
+	len = ARRAY_SIZE(init_gpio_mode_tegratab_common);
+	pins_info = init_gpio_mode_tegratab_common;
+
+	for (i = 0; i < len; ++i) {
+		tegra_gpio_init_configure(pins_info->gpio_nr,
+			pins_info->is_input, pins_info->value);
+		pins_info++;
+	}
+}
+
+int __init tegratab_pinmux_init(void)
+{
+	tegratab_gpio_init_configure();
+
+	tegra_pinmux_config_table(tegratab_pinmux_common,
+					ARRAY_SIZE(tegratab_pinmux_common));
+	tegra_drive_pinmux_config_table(tegratab_drive_pinmux,
+					ARRAY_SIZE(tegratab_drive_pinmux));
+	tegra_pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+	tegra_pinmux_config_table(manual_config_pinmux,
+		ARRAY_SIZE(manual_config_pinmux));
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-tegratab-power.c b/arch/arm/mach-tegra/board-tegratab-power.c
new file mode 100644
index 000000000000..db37ce08d0f5
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-power.c
@@ -0,0 +1,788 @@
+/*
+ * arch/arm/mach-tegra/board-tegratab-power.c
+ *
+ * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/pda_power.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/io.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/palmas.h>
+#include <linux/mfd/bq2419x.h>
+#include <linux/max17048_battery.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/regulator/userspace-consumer.h>
+
+#include <asm/mach-types.h>
+#include <linux/power/sbs-battery.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/edp.h>
+#include <mach/gpio-tegra.h>
+
+#include "cpu-tegra.h"
+#include "pm.h"
+#include "tegra-board-id.h"
+#include "board-pmu-defines.h"
+#include "board.h"
+#include "gpio-names.h"
+#include "board-common.h"
+#include "board-tegratab.h"
+#include "tegra_cl_dvfs.h"
+#include "devices.h"
+#include "tegra11_soctherm.h"
+#include "tegra3_tsensor.h"
+
+#define PMC_CTRL		0x0
+#define PMC_CTRL_INTR_LOW	(1 << 17)
+
+/* BQ2419X VBUS regulator */
+static struct regulator_consumer_supply tegratab_bq2419x_vbus_supply[] = {
+	REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
+};
+
+static struct regulator_consumer_supply tegratab_bq2419x_batt_supply[] = {
+	REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
+};
+
+static struct regulator_init_data tegratab_bq2419x_init_data = {
+	.constraints = {
+		.name = "bq2419x_vbus",
+		.min_uV = 0,
+		.max_uV = 5000000,
+		.valid_modes_mask = (REGULATOR_MODE_NORMAL |
+					REGULATOR_MODE_STANDBY),
+		.valid_ops_mask = (REGULATOR_CHANGE_MODE |
+					REGULATOR_CHANGE_STATUS |
+					REGULATOR_CHANGE_VOLTAGE),
+	},
+	.num_consumer_supplies = ARRAY_SIZE(tegratab_bq2419x_vbus_supply),
+	.consumer_supplies = tegratab_bq2419x_vbus_supply,
+};
+
+static struct bq2419x_regulator_platform_data tegratab_bq2419x_reg_pdata = {
+	.reg_init_data = &tegratab_bq2419x_init_data,
+	.gpio_otg_iusb = TEGRA_GPIO_PI4,
+	.power_off_on_suspend = true,
+};
+
+struct bq2419x_charger_platform_data tegratab_bq2419x_charger_pdata = {
+	.use_usb = 1,
+	.use_mains = 1,
+	.gpio_interrupt = TEGRA_GPIO_PJ0,
+	.gpio_status = TEGRA_GPIO_PK0,
+	.update_status = max17048_battery_status,
+	.battery_check = max17048_check_battery,
+	.max_charge_current_mA = 3000,
+	.charging_term_current_mA = 100,
+	.consumer_supplies = tegratab_bq2419x_batt_supply,
+	.num_consumer_supplies = ARRAY_SIZE(tegratab_bq2419x_batt_supply),
+};
+
+struct max17048_battery_model tegratab_max17048_mdata = {
+	.rcomp		= 152,
+	.soccheck_A	= 206,
+	.soccheck_B	= 208,
+	.bits		= 19,
+	.alert_threshold = 0x00,
+	.one_percent_alerts = 0x40,
+	.alert_on_reset = 0x40,
+	.rcomp_seg	= 0x0080,
+	.hibernate	= 0x3080,
+	.vreset		= 0x3c96,
+	.valert		= 0xD4AA,
+	.ocvtest	= 55744,
+	.data_tbl = {
+		0xA2, 0x80, 0xA8, 0xF0, 0xAE, 0xD0, 0xB0, 0x90,
+		0xB2, 0x60, 0xB3, 0xF0, 0xB5, 0x80, 0xB7, 0x20,
+		0xB8, 0xD0, 0xBC, 0x00, 0xBE, 0x20, 0xC0, 0x20,
+		0xC3, 0xD0, 0xC9, 0x80, 0xCE, 0xA0, 0xCF, 0xC0,
+		0x0A, 0x60, 0x0D, 0xE0, 0x1D, 0x00, 0x1D, 0xE0,
+		0x1F, 0xE0, 0x1F, 0xE0, 0x11, 0xC0, 0x11, 0x20,
+		0x14, 0x60, 0x0B, 0xE0, 0x14, 0x80, 0x14, 0xC0,
+		0x0E, 0x20, 0x12, 0xA0, 0x03, 0x60, 0x03, 0x60,
+	},
+};
+
+struct max17048_platform_data tegratab_max17048_pdata = {
+	.use_ac = 0,
+	.use_usb = 0,
+	.model_data = &tegratab_max17048_mdata,
+};
+
+static struct i2c_board_info __initdata tegratab_max17048_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("max17048", 0x36),
+		.platform_data	= &tegratab_max17048_pdata,
+	},
+};
+
+struct bq2419x_platform_data tegratab_bq2419x_pdata = {
+	.reg_pdata = &tegratab_bq2419x_reg_pdata,
+	.bcharger_pdata = &tegratab_bq2419x_charger_pdata,
+	.disable_watchdog = true,
+};
+
+static struct i2c_board_info __initdata tegratab_bq2419x_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("bq2419x", 0x6b),
+		.platform_data	= &tegratab_bq2419x_pdata,
+	},
+};
+
+/************************ Tegratab based regulator ****************/
+static struct regulator_consumer_supply palmas_smps123_supply[] = {
+	REGULATOR_SUPPLY("vdd_cpu", NULL),
+};
+
+static struct regulator_consumer_supply palmas_smps45_supply[] = {
+	REGULATOR_SUPPLY("vdd_core", NULL),
+	REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
+	REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
+};
+
+static struct regulator_consumer_supply palmas_smps6_supply[] = {
+	REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
+	REGULATOR_SUPPLY("avdd_lcd", NULL),
+	REGULATOR_SUPPLY("avdd", "spi0.0"),
+};
+
+static struct regulator_consumer_supply palmas_smps7_supply[] = {
+	REGULATOR_SUPPLY("vddio_ddr", NULL),
+};
+
+static struct regulator_consumer_supply palmas_smps8_supply[] = {
+	REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
+	REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
+	REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
+	REGULATOR_SUPPLY("avdd_osc", NULL),
+	REGULATOR_SUPPLY("vddio_sys", NULL),
+	REGULATOR_SUPPLY("vddio_bb", NULL),
+	REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
+	REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
+	REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
+	REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
+	REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
+	REGULATOR_SUPPLY("vddio_audio", NULL),
+	REGULATOR_SUPPLY("pwrdet_audio", NULL),
+	REGULATOR_SUPPLY("vddio_uart", NULL),
+	REGULATOR_SUPPLY("pwrdet_uart", NULL),
+	REGULATOR_SUPPLY("vddio_gmi", NULL),
+	REGULATOR_SUPPLY("vlogic", "0-0069"),
+	REGULATOR_SUPPLY("vid", "0-000d"),
+	REGULATOR_SUPPLY("vddio", "0-0078"),
+};
+
+static struct regulator_consumer_supply palmas_smps9_supply[] = {
+	REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
+};
+
+static struct regulator_consumer_supply palmas_smps10_supply[] = {
+};
+
+static struct regulator_consumer_supply palmas_ldo1_supply[] = {
+	REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
+	REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
+	REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
+	REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
+	REGULATOR_SUPPLY("avdd_pllm", NULL),
+	REGULATOR_SUPPLY("avdd_pllu", NULL),
+	REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
+	REGULATOR_SUPPLY("avdd_pllx", NULL),
+	REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
+	REGULATOR_SUPPLY("avdd_plle", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldo2_supply[] = {
+	REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
+	REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
+	REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
+	REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
+	REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
+};
+
+static struct regulator_consumer_supply palmas_ldo3_supply[] = {
+	REGULATOR_SUPPLY("vpp_fuse", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldo4_supply[] = {
+	REGULATOR_SUPPLY("dvdd", "2-0010"),
+};
+
+static struct regulator_consumer_supply palmas_ldo5_supply[] = {
+	REGULATOR_SUPPLY("vdd_af_cam1", NULL),
+	REGULATOR_SUPPLY("vdd", "2-000C"),
+};
+
+static struct regulator_consumer_supply palmas_ldo6_supply[] = {
+};
+
+static struct regulator_consumer_supply palmas_ldo7_supply[] = {
+	REGULATOR_SUPPLY("avdd", "2-0010"),
+};
+static struct regulator_consumer_supply palmas_ldo8_supply[] = {
+	REGULATOR_SUPPLY("vdd_rtc", NULL),
+};
+static struct regulator_consumer_supply palmas_ldo9_supply[] = {
+	REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
+	REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
+};
+static struct regulator_consumer_supply palmas_ldoln_supply[] = {
+	REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
+};
+
+static struct regulator_consumer_supply palmas_ldousb_supply[] = {
+	REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
+	REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
+	REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
+	REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
+	REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
+
+};
+
+static struct regulator_consumer_supply palmas_regen1_supply[] = {
+};
+
+static struct regulator_consumer_supply palmas_regen2_supply[] = {
+};
+
+PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0, 0);
+PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0, 0);
+PALMAS_PDATA_INIT(smps6, 3200,  3200, NULL, 0, 0, 1, NORMAL);
+PALMAS_PDATA_INIT(smps7, 1350,  1350, NULL, 0, 0, 1, NORMAL);
+PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL);
+PALMAS_PDATA_INIT(smps9, 2900,  2900, NULL, 1, 0, 1, NORMAL);
+PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0, 0);
+PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 1, 0, 1, 0);
+PALMAS_PDATA_INIT(ldo2, 1200,  1200, palmas_rails(smps7), 0, 1, 1, 0);
+PALMAS_PDATA_INIT(ldo3, 1800,  1800, NULL, 0, 0, 0, 0);
+PALMAS_PDATA_INIT(ldo4, 1200,  1200, palmas_rails(smps8), 0, 0, 0, 0);
+PALMAS_PDATA_INIT(ldo5, 2700,  2700, palmas_rails(smps9), 0, 0, 1, 0);
+PALMAS_PDATA_INIT(ldo6, 2850,  2850, palmas_rails(smps9), 1, 1, 1, 0);
+PALMAS_PDATA_INIT(ldo7, 2700,  2700, palmas_rails(smps9), 0, 0, 1, 0);
+PALMAS_PDATA_INIT(ldo8, 950,  950, NULL, 1, 1, 1, 0);
+PALMAS_PDATA_INIT(ldo9, 1800,  2900, palmas_rails(smps9), 0, 0, 1, 0);
+PALMAS_PDATA_INIT(ldoln, 3300,   3300, NULL, 0, 0, 1, 0);
+PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1, 0);
+PALMAS_PDATA_INIT(regen1, 4200,  4200, NULL, 0, 0, 0, 0);
+PALMAS_PDATA_INIT(regen2, 4200,  4200, palmas_rails(smps8), 0, 0, 0, 0);
+
+#define PALMAS_REG_PDATA(_sname) (&reg_idata_##_sname)
+static struct regulator_init_data *tegratab_reg_data[PALMAS_NUM_REGS] = {
+	NULL,
+	PALMAS_REG_PDATA(smps123),
+	NULL,
+	PALMAS_REG_PDATA(smps45),
+	NULL,
+	PALMAS_REG_PDATA(smps6),
+	PALMAS_REG_PDATA(smps7),
+	PALMAS_REG_PDATA(smps8),
+	PALMAS_REG_PDATA(smps9),
+	PALMAS_REG_PDATA(smps10),
+	PALMAS_REG_PDATA(ldo1),
+	PALMAS_REG_PDATA(ldo2),
+	PALMAS_REG_PDATA(ldo3),
+	PALMAS_REG_PDATA(ldo4),
+	PALMAS_REG_PDATA(ldo5),
+	PALMAS_REG_PDATA(ldo6),
+	PALMAS_REG_PDATA(ldo7),
+	PALMAS_REG_PDATA(ldo8),
+	PALMAS_REG_PDATA(ldo9),
+	PALMAS_REG_PDATA(ldoln),
+	PALMAS_REG_PDATA(ldousb),
+	PALMAS_REG_PDATA(regen1),
+	PALMAS_REG_PDATA(regen2),
+	NULL,
+	NULL,
+	NULL,
+};
+
+#define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,	\
+		_tstep, _vsel)						\
+	static struct palmas_reg_init reg_init_data_##_name = {		\
+		.warm_reset = _warm_reset,				\
+		.roof_floor =	_roof_floor,				\
+		.mode_sleep = _mode_sleep,		\
+		.tstep = _tstep,			\
+		.vsel = _vsel,		\
+	}
+
+PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
+PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldo3, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+
+#define PALMAS_REG_INIT_DATA(_sname) (&reg_init_data_##_sname)
+static struct palmas_reg_init *tegratab_reg_init[PALMAS_NUM_REGS] = {
+	PALMAS_REG_INIT_DATA(smps12),
+	PALMAS_REG_INIT_DATA(smps123),
+	PALMAS_REG_INIT_DATA(smps3),
+	PALMAS_REG_INIT_DATA(smps45),
+	PALMAS_REG_INIT_DATA(smps457),
+	PALMAS_REG_INIT_DATA(smps6),
+	PALMAS_REG_INIT_DATA(smps7),
+	PALMAS_REG_INIT_DATA(smps8),
+	PALMAS_REG_INIT_DATA(smps9),
+	PALMAS_REG_INIT_DATA(smps10),
+	PALMAS_REG_INIT_DATA(ldo1),
+	PALMAS_REG_INIT_DATA(ldo2),
+	PALMAS_REG_INIT_DATA(ldo3),
+	PALMAS_REG_INIT_DATA(ldo4),
+	PALMAS_REG_INIT_DATA(ldo5),
+	PALMAS_REG_INIT_DATA(ldo6),
+	PALMAS_REG_INIT_DATA(ldo7),
+	PALMAS_REG_INIT_DATA(ldo8),
+	PALMAS_REG_INIT_DATA(ldo9),
+	PALMAS_REG_INIT_DATA(ldoln),
+	PALMAS_REG_INIT_DATA(ldousb),
+};
+
+static struct palmas_pmic_platform_data pmic_platform = {
+	.enable_ldo8_tracking = true,
+	.disabe_ldo8_tracking_suspend = true,
+	.disable_smps10_boost_suspend = true,
+};
+
+static struct palmas_pinctrl_config palmas_pincfg[] = {
+	PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
+	PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+};
+
+static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
+	.pincfg = palmas_pincfg,
+	.num_pinctrl = ARRAY_SIZE(palmas_pincfg),
+	.dvfs1_enable = true,
+	.dvfs2_enable = false,
+};
+
+struct palmas_extcon_platform_data palmas_extcon_pdata = {
+	.connection_name = "palmas-extcon",
+	.enable_vbus_detection = true,
+	.enable_id_pin_detection = false,
+};
+
+static struct palmas_platform_data palmas_pdata = {
+	.gpio_base = PALMAS_TEGRA_GPIO_BASE,
+	.irq_base = PALMAS_TEGRA_IRQ_BASE,
+	.pmic_pdata = &pmic_platform,
+	.use_power_off = true,
+	.pinctrl_pdata = &palmas_pinctrl_pdata,
+	.extcon_pdata = &palmas_extcon_pdata,
+};
+
+static struct i2c_board_info palma_device[] = {
+	{
+		I2C_BOARD_INFO("tps65913", 0x58),
+		.irq		= INT_EXTERNAL_PMU,
+		.platform_data	= &palmas_pdata,
+	},
+};
+
+static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
+	REGULATOR_SUPPLY("dvdd_lcd", NULL),
+};
+
+static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
+	REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
+};
+
+/* EN_1V8_TS From TEGRA_GPIO_PH4 */
+static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
+	REGULATOR_SUPPLY("dvdd", "spi0.0"),
+};
+
+/* ENABLE 5v0 for HDMI */
+static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
+	REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
+};
+
+static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
+	REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
+};
+
+static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
+	REGULATOR_SUPPLY("dovdd", "2-0010"),
+};
+
+/* Macro for defining fixed regulator sub device data */
+#define FIXED_SUPPLY(_name) "fixed_reg_"#_name
+#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,	\
+	_gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)	\
+	static struct regulator_init_data ri_data_##_var =		\
+	{								\
+		.supply_regulator = _in_supply,				\
+		.num_consumer_supplies =				\
+			ARRAY_SIZE(fixed_reg_##_name##_supply),		\
+		.consumer_supplies = fixed_reg_##_name##_supply,	\
+		.constraints = {					\
+			.valid_modes_mask = (REGULATOR_MODE_NORMAL |	\
+					REGULATOR_MODE_STANDBY),	\
+			.valid_ops_mask = (REGULATOR_CHANGE_MODE |	\
+					REGULATOR_CHANGE_STATUS |	\
+					REGULATOR_CHANGE_VOLTAGE),	\
+			.always_on = _always_on,			\
+			.boot_on = _boot_on,				\
+		},							\
+	};								\
+	static struct fixed_voltage_config fixed_reg_##_var##_pdata =	\
+	{								\
+		.supply_name = FIXED_SUPPLY(_name),			\
+		.microvolts = _millivolts * 1000,			\
+		.gpio = _gpio_nr,					\
+		.gpio_is_open_drain = _open_drain,			\
+		.enable_high = _active_high,				\
+		.enabled_at_boot = _boot_state,				\
+		.init_data = &ri_data_##_var,				\
+	};								\
+	static struct platform_device fixed_reg_##_var##_dev = {	\
+		.name = "reg-fixed-voltage",				\
+		.id = _id,						\
+		.dev = {						\
+			.platform_data = &fixed_reg_##_var##_pdata,	\
+		},							\
+	}
+
+/*
+ * Creating the fixed regulator device table
+ */
+
+FIXED_REG(1,	dvdd_lcd_1v8,	dvdd_lcd_1v8,
+	palmas_rails(smps8),	0,	1,
+	PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,	false,	true,	1,	1800);
+
+FIXED_REG(2,	vdd_lcd_bl_en,	vdd_lcd_bl_en,
+	NULL,	0,	1,
+	TEGRA_GPIO_PH2,	false,	true,	1,	3700);
+
+FIXED_REG(3,	dvdd_ts,	dvdd_ts,
+	palmas_rails(smps8),	0,	0,
+	TEGRA_GPIO_PH4,	false,	false,	1,	1800);
+
+FIXED_REG(4,	vdd_hdmi_5v0,	vdd_hdmi_5v0,
+	palmas_rails(smps10),	0,	0,
+	TEGRA_GPIO_PK6,	false,	true,	0,	5000);
+
+FIXED_REG(5,	vddio_sd_slot,	vddio_sd_slot,
+	palmas_rails(smps9),	0,	0,
+	TEGRA_GPIO_PK1,	false,	true,	0,	2900);
+
+FIXED_REG(6,	vd_cam_1v8,	vd_cam_1v8,
+	palmas_rails(smps8),	0,	0,
+	PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,	false,	true,	0,	1800);
+
+#define ADD_FIXED_REG(_name)	(&fixed_reg_##_name##_dev)
+
+/* Gpio switch regulator platform data for Tegratab E1569 */
+static struct platform_device *fixed_reg_devs[] = {
+	ADD_FIXED_REG(dvdd_lcd_1v8),
+	ADD_FIXED_REG(vdd_lcd_bl_en),
+	ADD_FIXED_REG(dvdd_ts),
+	ADD_FIXED_REG(vdd_hdmi_5v0),
+	ADD_FIXED_REG(vddio_sd_slot),
+	ADD_FIXED_REG(vd_cam_1v8),
+};
+
+
+int __init tegratab_palmas_regulator_init(void)
+{
+	void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+	u32 pmc_ctrl;
+	int i;
+
+	/* TPS65913: Normal state of INT request line is LOW.
+	 * configure the power management controller to trigger PMU
+	 * interrupts when HIGH.
+	 */
+	pmc_ctrl = readl(pmc + PMC_CTRL);
+	writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+	for (i = 0; i < PALMAS_NUM_REGS ; i++) {
+		pmic_platform.reg_data[i] = tegratab_reg_data[i];
+		pmic_platform.reg_init[i] = tegratab_reg_init[i];
+	}
+
+	i2c_register_board_info(4, palma_device,
+			ARRAY_SIZE(palma_device));
+	return 0;
+}
+
+static int ac_online(void)
+{
+	return 1;
+}
+
+static struct resource tegratab_pda_resources[] = {
+	[0] = {
+		.name	= "ac",
+	},
+};
+
+static struct pda_power_pdata tegratab_pda_data = {
+	.is_ac_online	= ac_online,
+};
+
+static struct platform_device tegratab_pda_power_device = {
+	.name		= "pda-power",
+	.id		= -1,
+	.resource	= tegratab_pda_resources,
+	.num_resources	= ARRAY_SIZE(tegratab_pda_resources),
+	.dev	= {
+		.platform_data	= &tegratab_pda_data,
+	},
+};
+
+static struct tegra_suspend_platform_data tegratab_suspend_data = {
+	.cpu_timer	= 300,
+	.cpu_off_timer	= 300,
+	.suspend_mode	= TEGRA_SUSPEND_LP0,
+	.core_timer	= 0x157e,
+	.core_off_timer = 2000,
+	.corereq_high	= true,
+	.sysclkreq_high	= true,
+	.cpu_lp2_min_residency = 1000,
+	.min_residency_crail = 20000,
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
+	.lp1_lowvolt_support = false,
+	.i2c_base_addr = 0,
+	.pmuslave_addr = 0,
+	.core_reg_addr = 0,
+	.lp1_core_volt_low = 0,
+	.lp1_core_volt_high = 0,
+#endif
+};
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+/* board parameters for cpu dfll */
+static struct tegra_cl_dvfs_cfg_param tegratab_cl_dvfs_param = {
+	.sample_rate = 12500,
+
+	.force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
+	.cf = 10,
+	.ci = 0,
+	.cg = 2,
+
+	.droop_cut_value = 0xF,
+	.droop_restore_ramp = 0x0,
+	.scale_out_ramp = 0x0,
+};
+#endif
+
+/* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
+#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
+static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
+static inline void fill_reg_map(void)
+{
+	int i;
+	for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
+		pmu_cpu_vdd_map[i].reg_value = i + 0x10;
+		pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
+	}
+}
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+static struct tegra_cl_dvfs_platform_data tegratab_cl_dvfs_data = {
+	.dfll_clk_name = "dfll_cpu",
+	.pmu_if = TEGRA_CL_DVFS_PMU_I2C,
+	.u.pmu_i2c = {
+		.fs_rate = 400000,
+		.slave_addr = 0xb0,
+		.reg = 0x23,
+	},
+	.vdd_map = pmu_cpu_vdd_map,
+	.vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
+
+	.cfg_param = &tegratab_cl_dvfs_param,
+};
+
+static int __init tegratab_cl_dvfs_init(void)
+{
+	fill_reg_map();
+	if (tegra_revision < TEGRA_REVISION_A02)
+		tegratab_cl_dvfs_data.out_quiet_then_disable = true;
+	tegra_cl_dvfs_device.dev.platform_data = &tegratab_cl_dvfs_data;
+	platform_device_register(&tegra_cl_dvfs_device);
+
+	return 0;
+}
+#endif
+
+static int __init tegratab_fixed_regulator_init(void)
+{
+	if (!machine_is_tegratab())
+		return 0;
+
+	return platform_add_devices(fixed_reg_devs,
+			ARRAY_SIZE(fixed_reg_devs));
+}
+subsys_initcall_sync(tegratab_fixed_regulator_init);
+
+
+int __init tegratab_regulator_init(void)
+{
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+	tegratab_cl_dvfs_init();
+#endif
+	tegratab_palmas_regulator_init();
+
+	/* Disable charger when adapter is power source. */
+	if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY)
+		tegratab_bq2419x_pdata.bcharger_pdata = NULL;
+
+	i2c_register_board_info(0, tegratab_max17048_boardinfo, 1);
+	i2c_register_board_info(0, tegratab_bq2419x_boardinfo, 1);
+
+	platform_device_register(&tegratab_pda_power_device);
+
+	return 0;
+}
+
+int __init tegratab_suspend_init(void)
+{
+	tegra_init_suspend(&tegratab_suspend_data);
+	return 0;
+}
+
+int __init tegratab_edp_init(void)
+{
+	unsigned int regulator_mA;
+
+	regulator_mA = get_maximum_cpu_current_supported();
+	if (!regulator_mA)
+		regulator_mA = 15000;
+
+	pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
+	tegra_init_cpu_edp_limits(regulator_mA);
+
+	regulator_mA = get_maximum_core_current_supported();
+	if (!regulator_mA)
+		regulator_mA = 4000;
+
+	pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
+	tegra_init_core_edp_limits(regulator_mA);
+
+	return 0;
+}
+
+static struct thermal_zone_params tegratab_soctherm_therm_cpu_tzp = {
+	.governor_name = "pid_thermal_gov",
+};
+
+static struct tegra_tsensor_pmu_data tpdata_palmas = {
+	.reset_tegra = 1,
+	.pmu_16bit_ops = 0,
+	.controller_type = 0,
+	.pmu_i2c_addr = 0x58,
+	.i2c_controller_id = 4,
+	.poweroff_reg_addr = 0xa0,
+	.poweroff_reg_data = 0x0,
+};
+
+static struct soctherm_platform_data tegratab_soctherm_data = {
+	.therm = {
+		[THERM_CPU] = {
+			.zone_enable = true,
+			.passive_delay = 1000,
+			.hotspot_offset = 6000,
+			.num_trips = 3,
+			.trips = {
+				{
+					.cdev_type = "tegra-balanced",
+					.trip_temp = 90000,
+					.trip_type = THERMAL_TRIP_PASSIVE,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "tegra-heavy",
+					.trip_temp = 100000,
+					.trip_type = THERMAL_TRIP_HOT,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+				{
+					.cdev_type = "tegra-shutdown",
+					.trip_temp = 102000,
+					.trip_type = THERMAL_TRIP_CRITICAL,
+					.upper = THERMAL_NO_LIMIT,
+					.lower = THERMAL_NO_LIMIT,
+				},
+			},
+			.tzp = &tegratab_soctherm_therm_cpu_tzp,
+		},
+		[THERM_GPU] = {
+			.zone_enable = true,
+			.hotspot_offset = 6000,
+		},
+		[THERM_PLL] = {
+			.zone_enable = true,
+		},
+	},
+	.throttle = {
+		[THROTTLE_HEAVY] = {
+			.devs = {
+				[THROTTLE_DEV_CPU] = {
+					.enable = 1,
+				},
+			},
+		},
+	},
+	.tshut_pmu_trip_data = &tpdata_palmas,
+};
+
+int __init tegratab_soctherm_init(void)
+{
+	tegra_platform_edp_init(tegratab_soctherm_data.therm[THERM_CPU].trips,
+			&tegratab_soctherm_data.therm[THERM_CPU].num_trips,
+			8000); /* edp temperature margin */
+	tegra_add_tj_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
+			&tegratab_soctherm_data.therm[THERM_CPU].num_trips);
+	tegra_add_vc_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
+			&tegratab_soctherm_data.therm[THERM_CPU].num_trips);
+
+	return tegra11_soctherm_init(&tegratab_soctherm_data);
+}
diff --git a/arch/arm/mach-tegra/board-tegratab-powermon.c b/arch/arm/mach-tegra/board-tegratab-powermon.c
new file mode 100644
index 000000000000..e85d5735b494
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-powermon.c
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-tegra/board-tegratab-powermon.c
+ *
+ * Copyright (c) 2013, NVIDIA Corporation. All Rights Reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "board.h"
+#include "board-tegratab.h"
+
+int __init tegratab_pmon_init(void)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-tegratab-sdhci.c b/arch/arm/mach-tegra/board-tegratab-sdhci.c
new file mode 100644
index 000000000000..9e87e05861ef
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-sdhci.c
@@ -0,0 +1,270 @@
+/*
+ * arch/arm/mach-tegra/board-tegratab-sdhci.c
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/sdhci.h>
+#include <mach/gpio-tegra.h>
+#include <mach/io_dpd.h>
+#include <linux/wl12xx.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-tegratab.h"
+
+#define TEGRATAB_SD_CD	TEGRA_GPIO_PV2
+#define TEGRATAB_WLAN_PWR	TEGRA_GPIO_PCC5
+#define TEGRATAB_WLAN_RST	TEGRA_GPIO_PX7
+#define TEGRATAB_WLAN_WOW	TEGRA_GPIO_PU5
+static void (*wifi_status_cb)(int card_present, void *dev_id);
+static void *wifi_status_cb_devid;
+static int tegratab_wifi_status_register(void (*callback)(int , void *),
+					void *);
+
+static int tegratab_wifi_power(int on);
+static int tegratab_wifi_set_carddetect(int val);
+
+static struct wl12xx_platform_data tegratab_wl12xx_wlan_data __initdata = {
+	.board_ref_clock = WL12XX_REFCLOCK_26,
+	.board_tcxo_clock = 1,
+	.set_power = tegratab_wifi_power,
+	.set_carddetect = tegratab_wifi_set_carddetect,
+};
+
+static struct resource sdhci_resource0[] = {
+	[0] = {
+		.start  = INT_SDMMC1,
+		.end    = INT_SDMMC1,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_SDMMC1_BASE,
+		.end	= TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource sdhci_resource2[] = {
+	[0] = {
+		.start  = INT_SDMMC3,
+		.end    = INT_SDMMC3,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_SDMMC3_BASE,
+		.end	= TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource sdhci_resource3[] = {
+	[0] = {
+		.start  = INT_SDMMC4,
+		.end    = INT_SDMMC4,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_SDMMC4_BASE,
+		.end	= TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+static struct embedded_sdio_data embedded_sdio_data0 = {
+	.cccr   = {
+		.sdio_vsn       = 2,
+		.multi_block    = 1,
+		.low_speed      = 0,
+		.wide_bus       = 0,
+		.high_power     = 1,
+		.high_speed     = 1,
+	},
+	.cis  = {
+		.vendor	 = 0x02d0,
+		.device	 = 0x4329,
+	},
+};
+#endif
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
+	.mmc_data = {
+		.register_status_notify	= tegratab_wifi_status_register,
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+		.embedded_sdio = &embedded_sdio_data0,
+#endif
+		.built_in = 0,
+		.ocr_mask = MMC_OCR_1V8_MASK,
+	},
+#ifndef CONFIG_MMC_EMBEDDED_SDIO
+	.pm_flags = MMC_PM_KEEP_POWER,
+#endif
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+	.tap_delay = 0x2,
+	.trim_delay = 0x2,
+	.ddr_clk_limit = 41000000,
+	.uhs_mask = MMC_UHS_MASK_SDR104 |
+		MMC_UHS_MASK_DDR50,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+	.cd_gpio = TEGRATAB_SD_CD,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+	.tap_delay = 0x3,
+	.trim_delay = 0x3,
+	.ddr_clk_limit = 41000000,
+	.max_clk_limit = 82000000,
+	.sd_detect_in_suspend = 1,
+	.uhs_mask = MMC_UHS_MASK_DDR50,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+	.is_8bit = 1,
+	.tap_delay = 0x5,
+	.trim_delay = 0,
+	.ddr_clk_limit = 41000000,
+	.max_clk_limit = 156000000,
+	.mmc_data = {
+		.built_in = 1,
+		.ocr_mask = MMC_OCR_1V8_MASK,
+	},
+};
+
+static struct platform_device tegra_sdhci_device0 = {
+	.name		= "sdhci-tegra",
+	.id		= 0,
+	.resource	= sdhci_resource0,
+	.num_resources	= ARRAY_SIZE(sdhci_resource0),
+	.dev = {
+		.platform_data = &tegra_sdhci_platform_data0,
+	},
+};
+
+static struct platform_device tegra_sdhci_device2 = {
+	.name		= "sdhci-tegra",
+	.id		= 2,
+	.resource	= sdhci_resource2,
+	.num_resources	= ARRAY_SIZE(sdhci_resource2),
+	.dev = {
+		.platform_data = &tegra_sdhci_platform_data2,
+	},
+};
+
+static struct platform_device tegra_sdhci_device3 = {
+	.name		= "sdhci-tegra",
+	.id		= 3,
+	.resource	= sdhci_resource3,
+	.num_resources	= ARRAY_SIZE(sdhci_resource3),
+	.dev = {
+		.platform_data = &tegra_sdhci_platform_data3,
+	},
+};
+
+static int tegratab_wifi_status_register(
+		void (*callback)(int card_present, void *dev_id),
+		void *dev_id)
+{
+	if (wifi_status_cb)
+		return -EAGAIN;
+	wifi_status_cb = callback;
+	wifi_status_cb_devid = dev_id;
+	return 0;
+}
+
+static int tegratab_wifi_set_carddetect(int val)
+{
+	pr_debug("%s: %d\n", __func__, val);
+	if (wifi_status_cb)
+		wifi_status_cb(val, wifi_status_cb_devid);
+	else
+		pr_warning("%s: Nobody to notify\n", __func__);
+	return 0;
+}
+
+static int tegratab_wifi_power(int on)
+{
+	pr_debug("%s: %d\n", __func__, on);
+
+	if (on) {
+		gpio_set_value(TEGRATAB_WLAN_RST, 1);
+		mdelay(100);
+		gpio_set_value(TEGRATAB_WLAN_RST, 0);
+		mdelay(100);
+		gpio_set_value(TEGRATAB_WLAN_RST, 1);
+		mdelay(100);
+		gpio_set_value(TEGRATAB_WLAN_PWR, 1);
+		mdelay(200);
+	} else {
+		gpio_set_value(TEGRATAB_WLAN_RST, 0);
+		mdelay(100);
+		gpio_set_value(TEGRATAB_WLAN_PWR, 0);
+	}
+
+	return 0;
+}
+
+static int __init tegratab_wifi_init(void)
+{
+	int rc;
+
+	rc = gpio_request(TEGRATAB_WLAN_PWR, "wlan_power");
+	if (rc)
+		pr_err("WLAN_PWR gpio request failed:%d\n", rc);
+	rc = gpio_request(TEGRATAB_WLAN_RST, "wlan_rst");
+	if (rc)
+		pr_err("WLAN_RST gpio request failed:%d\n", rc);
+	rc = gpio_request(TEGRATAB_WLAN_WOW, "bcmsdh_sdmmc");
+	if (rc)
+		pr_err("WLAN_WOW gpio request failed:%d\n", rc);
+
+	rc = gpio_direction_output(TEGRATAB_WLAN_PWR, 0);
+	if (rc)
+		pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc);
+	rc = gpio_direction_output(TEGRATAB_WLAN_RST, 0);
+	if (rc)
+		pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc);
+	rc = gpio_direction_input(TEGRATAB_WLAN_WOW);
+	if (rc)
+		pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc);
+	tegratab_wl12xx_wlan_data.irq = gpio_to_irq(TEGRATAB_WLAN_WOW);
+		wl12xx_set_platform_data(&tegratab_wl12xx_wlan_data);
+	return 0;
+}
+
+int __init tegratab_sdhci_init(void)
+{
+	platform_device_register(&tegra_sdhci_device3);
+	platform_device_register(&tegra_sdhci_device2);
+	platform_device_register(&tegra_sdhci_device0);
+	tegratab_wifi_init();
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-tegratab-sensors.c b/arch/arm/mach-tegra/board-tegratab-sensors.c
new file mode 100644
index 000000000000..4ae1ced9b210
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab-sensors.c
@@ -0,0 +1,561 @@
+/*
+ * arch/arm/mach-tegra/board-tegratab-sensors.c
+ *
+ * Copyright (c) 2012-2013 NVIDIA CORPORATION, All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of NVIDIA CORPORATION nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/mpu.h>
+#include <linux/regulator/consumer.h>
+#include <linux/gpio.h>
+#include <linux/therm_est.h>
+#include <linux/nct1008.h>
+#include <linux/cm3217.h>
+#include <mach/edp.h>
+#include <linux/edp.h>
+#include <mach/gpio-tegra.h>
+#include <mach/pinmux-t11.h>
+#include <mach/pinmux.h>
+#include <media/ov5693.h>
+#include <media/ad5823.h>
+#include <generated/mach-types.h>
+#include <linux/power/sbs-battery.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-common.h"
+#include "board-tegratab.h"
+#include "cpu-tegra.h"
+#include "devices.h"
+#include "tegra-board-id.h"
+#include "dvfs.h"
+
+static struct board_info board_info;
+
+static struct throttle_table tj_throttle_table[] = {
+		/* CPU_THROT_LOW cannot be used by other than CPU */
+		/* NO_CAP cannot be used by CPU */
+		/*    CPU,   C2BUS,   C3BUS,    SCLK,     EMC */
+		{ { 1530000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1428000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1326000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1224000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1122000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1020000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  918000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  816000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  714000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  564000,  564000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  528000,  528000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  492000,  492000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  420000,  420000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  408000,  408000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  360000,  360000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  360000,  360000,  312000,  NO_CAP } },
+		{ {  510000,  360000,  360000,  312000,  480000 } },
+		{ {  468000,  360000,  360000,  312000,  480000 } },
+		{ {  468000,  276000,  276000,  208000,  480000 } },
+		{ {  372000,  276000,  276000,  208000,  204000 } },
+		{ {  288000,  276000,  276000,  208000,  204000 } },
+		{ {  252000,  276000,  228000,  208000,  102000 } },
+		{ {  204000,  276000,  228000,  208000,  102000 } },
+		{ {  102000,  276000,  228000,  208000,  102000 } },
+	  { { CPU_THROT_LOW,  276000,  228000,  208000,  102000 } },
+};
+
+static struct balanced_throttle tj_throttle = {
+	.throt_tab_size = ARRAY_SIZE(tj_throttle_table),
+	.throt_tab = tj_throttle_table,
+};
+
+static int __init tegratab_throttle_init(void)
+{
+	if (machine_is_tegratab())
+		balanced_throttle_register(&tj_throttle, "tegra-balanced");
+	return 0;
+}
+module_init(tegratab_throttle_init);
+
+static struct nct1008_platform_data tegratab_nct1008_pdata = {
+	.supported_hwrev = true,
+	.ext_range = true,
+	.conv_rate = 0x08,
+	.shutdown_ext_limit = 105, /* C */
+	.shutdown_local_limit = 120, /* C */
+};
+
+static struct i2c_board_info tegratab_i2c4_nct1008_board_info[] = {
+	{
+		I2C_BOARD_INFO("nct1008", 0x4C),
+		.platform_data = &tegratab_nct1008_pdata,
+		.irq = -1,
+	}
+};
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.od		= TEGRA_PIN_OD_DEFAULT,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_##_ioreset	\
+}
+
+static struct tegra_pingroup_config mclk_disable =
+	VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config mclk_enable =
+	VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config pbb0_disable =
+	VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+/*
+static struct tegra_pingroup_config pbb0_enable =
+	VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+*/
+/*
+ * As a workaround, tegratab_vcmvdd need to be allocated to activate the
+ * sensor devices. This is due to the focuser device(AD5823) will hook up
+ * the i2c bus if it is not powered up.
+*/
+static struct regulator *tegratab_vcmvdd;
+
+static int tegratab_get_vcmvdd(void)
+{
+	if (!tegratab_vcmvdd) {
+		tegratab_vcmvdd = regulator_get(NULL, "vdd_af_cam1");
+		if (unlikely(WARN_ON(IS_ERR(tegratab_vcmvdd)))) {
+			pr_err("%s: can't get regulator vcmvdd: %ld\n",
+				__func__, PTR_ERR(tegratab_vcmvdd));
+			tegratab_vcmvdd = NULL;
+			return -ENODEV;
+		}
+	}
+	return 0;
+}
+
+static int tegratab_ov5693_power_on(struct ov5693_power_rail *pw)
+{
+	int err;
+
+	if (unlikely(!pw || !pw->avdd || !pw->dovdd))
+		return -EFAULT;
+
+	if (tegratab_get_vcmvdd())
+		goto ov5693_poweron_fail;
+
+	gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+	usleep_range(10, 20);
+
+	err = regulator_enable(pw->avdd);
+	if (err)
+		goto ov5693_avdd_fail;
+
+	err = regulator_enable(pw->dovdd);
+	if (err)
+		goto ov5693_iovdd_fail;
+
+	usleep_range(1, 2);
+	gpio_set_value(CAM1_POWER_DWN_GPIO, 1);
+
+	err = regulator_enable(tegratab_vcmvdd);
+	if (unlikely(err))
+		goto ov5693_vcmvdd_fail;
+
+	tegra_pinmux_config_table(&mclk_enable, 1);
+	usleep_range(300, 310);
+
+	return 0;
+
+ov5693_vcmvdd_fail:
+	regulator_disable(pw->dovdd);
+
+ov5693_iovdd_fail:
+	regulator_disable(pw->avdd);
+
+ov5693_avdd_fail:
+	gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+
+ov5693_poweron_fail:
+	pr_err("%s FAILED\n", __func__);
+	return -ENODEV;
+}
+
+static int tegratab_ov5693_power_off(struct ov5693_power_rail *pw)
+{
+	if (unlikely(!pw || !tegratab_vcmvdd || !pw->avdd || !pw->dovdd))
+		return -EFAULT;
+
+	usleep_range(21, 25);
+	tegra_pinmux_config_table(&mclk_disable, 1);
+	gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+	usleep_range(1, 2);
+
+	regulator_disable(tegratab_vcmvdd);
+	regulator_disable(pw->dovdd);
+	regulator_disable(pw->avdd);
+
+	return 0;
+}
+
+static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
+	{ OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
+};
+static struct ov5693_platform_data tegratab_ov5693_pdata = {
+	.num		= 0,
+	.dev_name	= "camera",
+	.gpio_count	= ARRAY_SIZE(ov5693_gpio_pdata),
+	.gpio		= ov5693_gpio_pdata,
+	.power_on	= tegratab_ov5693_power_on,
+	.power_off	= tegratab_ov5693_power_off,
+};
+
+static int tegratab_ad5823_power_on(struct ad5823_platform_data *pdata)
+{
+	int err = 0;
+
+	pr_info("%s\n", __func__);
+	err = gpio_request_one(pdata->gpio, GPIOF_OUT_INIT_LOW, "af_pwdn");
+
+	gpio_set_value_cansleep(pdata->gpio, 1);
+
+	return err;
+}
+
+static int tegratab_ad5823_power_off(struct ad5823_platform_data *pdata)
+{
+	pr_info("%s\n", __func__);
+	gpio_set_value_cansleep(pdata->gpio, 0);
+	gpio_free(pdata->gpio);
+	return 0;
+}
+
+static struct ad5823_platform_data tegratab_ad5823_pdata = {
+	.gpio = CAM_AF_PWDN,
+	.power_on	= tegratab_ad5823_power_on,
+	.power_off	= tegratab_ad5823_power_off,
+};
+
+static struct i2c_board_info tegratab_i2c_board_info_e1599[] = {
+	{
+		I2C_BOARD_INFO("ov5693", 0x10),
+		.platform_data = &tegratab_ov5693_pdata,
+	},
+	{
+		I2C_BOARD_INFO("ad5823", 0x0c),
+		.platform_data = &tegratab_ad5823_pdata,
+	},
+};
+
+static int tegratab_camera_init(void)
+{
+	tegra_pinmux_config_table(&mclk_disable, 1);
+	tegra_pinmux_config_table(&pbb0_disable, 1);
+
+	i2c_register_board_info(2, tegratab_i2c_board_info_e1599,
+		ARRAY_SIZE(tegratab_i2c_board_info_e1599));
+	return 0;
+}
+
+/* MPU board file definition	*/
+static struct mpu_platform_data mpu6050_gyro_data = {
+	.int_config	= 0x10,
+	.level_shifter	= 0,
+	/* Located in board_[platformname].h */
+	.orientation	= MPU_GYRO_ORIENTATION,
+	.sec_slave_type	= SECONDARY_SLAVE_TYPE_COMPASS,
+	.sec_slave_id	= COMPASS_ID_AK8975,
+	.secondary_i2c_addr	= MPU_COMPASS_ADDR,
+	.secondary_read_reg	= 0x06,
+	.secondary_orientation	= MPU_COMPASS_ORIENTATION,
+	.key		= {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
+			   0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
+};
+
+#define TEGRA_CAMERA_GPIO(_gpio, _label, _value)		\
+	{							\
+		.gpio = _gpio,					\
+		.label = _label,				\
+		.value = _value,				\
+	}
+
+static struct cm3217_platform_data tegratab_cm3217_pdata = {
+	.levels = {10, 160, 225, 320, 640, 1280, 2600, 5800, 8000, 10240},
+	.golden_adc = 0,
+	.power = 0,
+};
+
+static struct i2c_board_info tegratab_i2c0_board_info_cm3217[] = {
+	{
+		I2C_BOARD_INFO("cm3217", 0x10),
+		.platform_data = &tegratab_cm3217_pdata,
+	},
+};
+
+static struct i2c_board_info __initdata inv_mpu6050_i2c2_board_info[] = {
+	{
+		I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
+		.platform_data = &mpu6050_gyro_data,
+	},
+};
+
+static void mpuirq_init(void)
+{
+	int ret = 0;
+	unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
+	unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
+	char *gyro_name = MPU_GYRO_NAME;
+
+	pr_info("*** MPU START *** mpuirq_init...\n");
+
+	ret = gpio_request(gyro_irq_gpio, gyro_name);
+
+	if (ret < 0) {
+		pr_err("%s: gpio_request failed %d\n", __func__, ret);
+		return;
+	}
+
+	ret = gpio_direction_input(gyro_irq_gpio);
+	if (ret < 0) {
+		pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
+		gpio_free(gyro_irq_gpio);
+		return;
+	}
+	pr_info("*** MPU END *** mpuirq_init...\n");
+
+	inv_mpu6050_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
+	i2c_register_board_info(gyro_bus_num, inv_mpu6050_i2c2_board_info,
+		ARRAY_SIZE(inv_mpu6050_i2c2_board_info));
+}
+
+static int tegratab_nct1008_init(void)
+{
+	int nct1008_port;
+	int ret = 0;
+
+	nct1008_port = TEGRA_GPIO_PO4;
+
+	tegra_add_cdev_trips(tegratab_nct1008_pdata.trips,
+				&tegratab_nct1008_pdata.num_trips);
+
+	tegratab_i2c4_nct1008_board_info[0].irq = gpio_to_irq(nct1008_port);
+	pr_info("%s: tegratab nct1008 irq %d", __func__, \
+				tegratab_i2c4_nct1008_board_info[0].irq);
+
+	ret = gpio_request(nct1008_port, "temp_alert");
+	if (ret < 0)
+		return ret;
+
+	ret = gpio_direction_input(nct1008_port);
+	if (ret < 0) {
+		pr_info("%s: calling gpio_free(nct1008_port)", __func__);
+		gpio_free(nct1008_port);
+	}
+
+	/* tegratab has thermal sensor on GEN1-I2C i.e. instance 0 */
+	i2c_register_board_info(0, tegratab_i2c4_nct1008_board_info,
+		ARRAY_SIZE(tegratab_i2c4_nct1008_board_info));
+
+	return ret;
+}
+
+#ifdef CONFIG_TEGRA_SKIN_THROTTLE
+static struct thermal_trip_info skin_trips[] = {
+	{
+		.cdev_type = "skin-balanced",
+		.trip_temp = 45000,
+		.trip_type = THERMAL_TRIP_PASSIVE,
+		.upper = THERMAL_NO_LIMIT,
+		.lower = THERMAL_NO_LIMIT,
+		.hysteresis = 0,
+	},
+};
+
+static struct therm_est_subdevice skin_devs[] = {
+	{
+		.dev_data = "nct_ext",
+		.coeffs = {
+			2, 1, 1, 1,
+			1, 1, 1, 1,
+			1, 1, 1, 0,
+			1, 1, 0, 0,
+			0, 0, -1, -7
+		},
+	},
+	{
+		.dev_data = "nct_int",
+		.coeffs = {
+			-11, -7, -5, -3,
+			-3, -2, -1, 0,
+			0, 0, 1, 1,
+			1, 2, 2, 3,
+			4, 6, 11, 18
+		},
+	},
+};
+
+static struct therm_est_data skin_data = {
+	.num_trips = ARRAY_SIZE(skin_trips),
+	.trips = skin_trips,
+	.toffset = 9793,
+	.polling_period = 1100,
+	.passive_delay = 15000,
+	.tc1 = 10,
+	.tc2 = 1,
+	.ndevs = ARRAY_SIZE(skin_devs),
+	.devs = skin_devs,
+};
+
+static struct throttle_table skin_throttle_table[] = {
+		/* CPU_THROT_LOW cannot be used by other than CPU */
+		/* NO_CAP cannot be used by CPU */
+		/*    CPU,   C2BUS,   C3BUS,    SCLK,     EMC */
+		{ { 1530000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1530000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1326000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1326000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1326000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1326000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1326000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1122000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1122000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1122000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1122000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1122000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1122000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1020000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1020000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1020000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1020000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1020000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ { 1020000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  918000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  918000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  918000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  918000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  918000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  918000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  816000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  816000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  816000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  816000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  816000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  816000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  714000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  714000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  714000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  714000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  714000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  714000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  NO_CAP,  NO_CAP,  NO_CAP,  NO_CAP } },
+		{ {  612000,  564000,  564000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  564000,  564000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  528000,  528000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  528000,  528000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  492000,  492000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  492000,  492000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  420000,  420000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  420000,  420000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  408000,  408000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  408000,  408000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  360000,  360000,  NO_CAP,  NO_CAP } },
+		{ {  612000,  360000,  360000,  NO_CAP,  NO_CAP } },
+		{ {  510000,  360000,  360000,  312000,  NO_CAP } },
+		{ {  510000,  360000,  360000,  312000,  NO_CAP } },
+		{ {  510000,  360000,  360000,  312000,  480000 } },
+		{ {  510000,  360000,  360000,  312000,  480000 } },
+		{ {  510000,  360000,  360000,  312000,  480000 } },
+		{ {  510000,  360000,  360000,  312000,  480000 } },
+		{ {  510000,  360000,  360000,  312000,  480000 } },
+		{ {  510000,  360000,  360000,  312000,  480000 } },
+		{ {  468000,  360000,  360000,  312000,  480000 } },
+		{ {  468000,  360000,  360000,  312000,  480000 } },
+		{ {  468000,  276000,  276000,  208000,  480000 } },
+		{ {  468000,  276000,  276000,  208000,  480000 } },
+		{ {  372000,  276000,  276000,  208000,  204000 } },
+		{ {  372000,  276000,  276000,  208000,  204000 } },
+		{ {  288000,  276000,  276000,  208000,  204000 } },
+		{ {  288000,  276000,  276000,  208000,  204000 } },
+		{ {  252000,  276000,  228000,  208000,  102000 } },
+		{ {  252000,  276000,  228000,  208000,  102000 } },
+		{ {  204000,  276000,  228000,  208000,  102000 } },
+		{ {  204000,  276000,  228000,  208000,  102000 } },
+		{ {  102000,  276000,  228000,  208000,  102000 } },
+	  { { CPU_THROT_LOW,  276000,  228000,  208000,  102000 } },
+};
+
+static struct balanced_throttle skin_throttle = {
+	.throt_tab_size = ARRAY_SIZE(skin_throttle_table),
+	.throt_tab = skin_throttle_table,
+};
+
+static int __init tegratab_skin_init(void)
+{
+	if (machine_is_tegratab()) {
+		balanced_throttle_register(&skin_throttle, "skin-balanced");
+		tegra_skin_therm_est_device.dev.platform_data = &skin_data;
+		platform_device_register(&tegra_skin_therm_est_device);
+	}
+
+	return 0;
+}
+late_initcall(tegratab_skin_init);
+#endif
+
+int __init tegratab_sensors_init(void)
+{
+	int err;
+
+	tegra_get_board_info(&board_info);
+
+	/* E1545+E1604 has no temp sensor. */
+	if (board_info.board_id != BOARD_E1545) {
+		err = tegratab_nct1008_init();
+		if (err) {
+			pr_err("%s: nct1008 register failed.\n", __func__);
+			return err;
+		}
+	}
+
+	tegratab_camera_init();
+	mpuirq_init();
+
+	i2c_register_board_info(0, tegratab_i2c0_board_info_cm3217,
+				ARRAY_SIZE(tegratab_i2c0_board_info_cm3217));
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-tegratab.c b/arch/arm/mach-tegra/board-tegratab.c
new file mode 100644
index 000000000000..2ff98c8febd3
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab.c
@@ -0,0 +1,735 @@
+/*
+ * arch/arm/mach-tegra/board-tegratab.c
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/platform_data/tegra_usb_modem_power.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/rm31080a_ts.h>
+#include <linux/tegra_uart.h>
+#include <linux/memblock.h>
+#include <linux/spi-tegra.h>
+#include <linux/skbuff.h>
+#include <linux/ti_wilink_st.h>
+#include <linux/regulator/consumer.h>
+#include <linux/smb349-charger.h>
+#include <linux/max17048_battery.h>
+#include <linux/leds.h>
+#include <linux/i2c/at24.h>
+#include <linux/of_platform.h>
+#include <linux/edp.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-tegra30.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/io_dpd.h>
+#include <mach/i2s.h>
+#include <mach/tegra_asoc_pdata.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+#include <mach/gpio-tegra.h>
+#include <mach/tegra_fiq_debugger.h>
+#include <mach/hardware.h>
+
+#include "board-touch-raydium.h"
+#include "board.h"
+#include "board-common.h"
+#include "clock.h"
+#include "board-tegratab.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "fuse.h"
+#include "pm.h"
+#include "pm-irq.h"
+#include "common.h"
+#include "tegra-board-id.h"
+
+#if defined CONFIG_TI_ST || defined CONFIG_TI_ST_MODULE
+struct ti_st_plat_data tegratab_wilink_pdata = {
+	.nshutdown_gpio = TEGRA_GPIO_PQ7,
+	.dev_name = BLUETOOTH_UART_DEV_NAME,
+	.flow_cntrl = 1,
+	.baud_rate = 3000000,
+};
+
+static struct platform_device wl128x_device = {
+	.name           = "kim",
+	.id             = -1,
+	.dev.platform_data = &tegratab_wilink_pdata,
+};
+
+static struct platform_device btwilink_device = {
+	.name = "btwilink",
+	.id = -1,
+};
+
+static noinline void __init tegratab_bt_st(void)
+{
+	pr_info("tegratab_bt_st");
+
+	platform_device_register(&wl128x_device);
+	platform_device_register(&btwilink_device);
+}
+
+static struct resource tegratab_st_host_wake_resources[] = {
+	[0] = {
+		.name = "host_wake",
+		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+	},
+};
+
+static struct platform_device tegratab_st_host_wake_device = {
+	.name           = "st_host_wake",
+	.id             = 0,
+	.num_resources  = ARRAY_SIZE(tegratab_st_host_wake_resources),
+	.resource       = tegratab_st_host_wake_resources,
+};
+
+static noinline void __init tegratab_tegra_setup_st_host_wake(void)
+{
+	tegratab_st_host_wake_resources[0].start =
+		tegratab_st_host_wake_resources[0].end =
+		gpio_to_irq(TEGRA_GPIO_PU6);
+	platform_device_register(&tegratab_st_host_wake_device);
+}
+#endif
+
+static __initdata struct tegra_clk_init_table tegratab_clk_init_table[] = {
+	/* name		parent		rate		enabled */
+	{ "pll_m",	NULL,		0,		false},
+	{ "hda",	"pll_p",	108000000,	false},
+	{ "hda2codec_2x", "pll_p",	48000000,	false},
+	{ "pwm",	"pll_p",	3187500,	false},
+	{ "blink",	"clk_32k",	32768,		true},
+	{ "i2s1",	"pll_a_out0",	0,		false},
+	{ "i2s3",	"pll_a_out0",	0,		false},
+	{ "i2s4",	"pll_a_out0",	0,		false},
+	{ "spdif_out",	"pll_a_out0",	0,		false},
+	{ "d_audio",	"clk_m",	12000000,	false},
+	{ "dam0",	"clk_m",	12000000,	false},
+	{ "dam1",	"clk_m",	12000000,	false},
+	{ "dam2",	"clk_m",	12000000,	false},
+	{ "audio1",	"i2s1_sync",	0,		false},
+	{ "audio3",	"i2s3_sync",	0,		false},
+	/* Setting vi_sensor-clk to true for validation purpose, will imapact
+	 * power, later set to be false.*/
+	{ "vi_sensor",	"pll_p",	150000000,	false},
+	{ "cilab",	"pll_p",	150000000,	false},
+	{ "cilcd",	"pll_p",	150000000,	false},
+	{ "cile",	"pll_p",	150000000,	false},
+	{ "i2c1",	"pll_p",	3200000,	false},
+	{ "i2c2",	"pll_p",	3200000,	false},
+	{ "i2c3",	"pll_p",	3200000,	false},
+	{ "i2c4",	"pll_p",	3200000,	false},
+	{ "i2c5",	"pll_p",	3200000,	false},
+	{ NULL,		NULL,		0,		0},
+};
+
+static struct tegra_i2c_platform_data tegratab_i2c1_platform_data = {
+	.adapter_nr	= 0,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 100000, 0 },
+	.scl_gpio		= {TEGRA_GPIO_I2C1_SCL, 0},
+	.sda_gpio		= {TEGRA_GPIO_I2C1_SDA, 0},
+	.arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data tegratab_i2c2_platform_data = {
+	.adapter_nr	= 1,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 100000, 0 },
+	.is_clkon_always = true,
+	.scl_gpio		= {TEGRA_GPIO_I2C2_SCL, 0},
+	.sda_gpio		= {TEGRA_GPIO_I2C2_SDA, 0},
+	.arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data tegratab_i2c3_platform_data = {
+	.adapter_nr	= 2,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 100000, 0 },
+	.scl_gpio		= {TEGRA_GPIO_I2C3_SCL, 0},
+	.sda_gpio		= {TEGRA_GPIO_I2C3_SDA, 0},
+	.arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data tegratab_i2c4_platform_data = {
+	.adapter_nr	= 3,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 10000, 0 },
+	.scl_gpio		= {TEGRA_GPIO_I2C4_SCL, 0},
+	.sda_gpio		= {TEGRA_GPIO_I2C4_SDA, 0},
+	.arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data tegratab_i2c5_platform_data = {
+	.adapter_nr	= 4,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 400000, 0 },
+	.scl_gpio		= {TEGRA_GPIO_I2C5_SCL, 0},
+	.sda_gpio		= {TEGRA_GPIO_I2C5_SDA, 0},
+	.arb_recovery = arb_lost_recovery,
+};
+
+static struct i2c_board_info __initdata rt5640_board_info = {
+	I2C_BOARD_INFO("rt5640", 0x1c),
+};
+
+static void tegratab_i2c_init(void)
+{
+	struct board_info board_info;
+
+	tegra_get_board_info(&board_info);
+	tegra11_i2c_device1.dev.platform_data = &tegratab_i2c1_platform_data;
+	tegra11_i2c_device2.dev.platform_data = &tegratab_i2c2_platform_data;
+	tegra11_i2c_device3.dev.platform_data = &tegratab_i2c3_platform_data;
+	tegra11_i2c_device4.dev.platform_data = &tegratab_i2c4_platform_data;
+	tegra11_i2c_device5.dev.platform_data = &tegratab_i2c5_platform_data;
+
+	platform_device_register(&tegra11_i2c_device5);
+	platform_device_register(&tegra11_i2c_device4);
+	platform_device_register(&tegra11_i2c_device3);
+	platform_device_register(&tegra11_i2c_device2);
+	platform_device_register(&tegra11_i2c_device1);
+
+	i2c_register_board_info(0, &rt5640_board_info, 1);
+}
+
+static struct platform_device *tegratab_uart_devices[] __initdata = {
+	&tegra_uarta_device,
+	&tegra_uartb_device,
+	&tegra_uartc_device,
+	&tegra_uartd_device,
+};
+static struct uart_clk_parent uart_parent_clk[] = {
+	[0] = {.name = "clk_m"},
+	[1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+	[2] = {.name = "pll_m"},
+#endif
+};
+
+static struct tegra_uart_platform_data tegratab_uart_pdata;
+static struct tegra_uart_platform_data tegratab_loopback_uart_pdata;
+
+static void __init uart_debug_init(void)
+{
+	int debug_port_id;
+
+	debug_port_id = uart_console_debug_init(3);
+	if (debug_port_id < 0)
+		return;
+
+	tegratab_uart_devices[debug_port_id] = uart_console_debug_device;
+}
+
+static void __init tegratab_uart_init(void)
+{
+	struct clk *c;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
+		c = tegra_get_clock_by_name(uart_parent_clk[i].name);
+		if (IS_ERR_OR_NULL(c)) {
+			pr_err("Not able to get the clock for %s\n",
+						uart_parent_clk[i].name);
+			continue;
+		}
+		uart_parent_clk[i].parent_clk = c;
+		uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+	}
+	tegratab_uart_pdata.parent_clk_list = uart_parent_clk;
+	tegratab_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
+	tegratab_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
+	tegratab_loopback_uart_pdata.parent_clk_count =
+						ARRAY_SIZE(uart_parent_clk);
+	tegratab_loopback_uart_pdata.is_loopback = true;
+	tegra_uarta_device.dev.platform_data = &tegratab_uart_pdata;
+	tegra_uartb_device.dev.platform_data = &tegratab_uart_pdata;
+	tegra_uartc_device.dev.platform_data = &tegratab_uart_pdata;
+	tegra_uartd_device.dev.platform_data = &tegratab_uart_pdata;
+
+	/* Register low speed only if it is selected */
+	if (!is_tegra_debug_uartport_hs())
+		uart_debug_init();
+
+	platform_add_devices(tegratab_uart_devices,
+				ARRAY_SIZE(tegratab_uart_devices));
+}
+
+static struct resource tegra_rtc_resources[] = {
+	[0] = {
+		.start = TEGRA_RTC_BASE,
+		.end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = INT_RTC,
+		.end = INT_RTC,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device tegra_rtc_device = {
+	.name = "tegra_rtc",
+	.id   = -1,
+	.resource = tegra_rtc_resources,
+	.num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+
+static struct tegra_asoc_platform_data tegratab_audio_pdata = {
+	.gpio_spkr_en		= TEGRA_GPIO_SPKR_EN,
+	.gpio_hp_det		= TEGRA_GPIO_HP_DET,
+	.gpio_hp_mute		= -1,
+	.gpio_int_mic_en	= TEGRA_GPIO_INT_MIC_EN,
+	.gpio_ext_mic_en	= TEGRA_GPIO_EXT_MIC_EN,
+	.gpio_ldo1_en		= TEGRA_GPIO_LDO1_EN,
+	.gpio_codec1 = TEGRA_GPIO_CODEC1_EN,
+	.gpio_codec2 = TEGRA_GPIO_CODEC2_EN,
+	.gpio_codec3 = TEGRA_GPIO_CODEC3_EN,
+	.i2s_param[HIFI_CODEC]	= {
+		.audio_port_id	= 1,
+		.is_i2s_master	= 1,
+		.i2s_mode	= TEGRA_DAIFMT_I2S,
+	},
+	.i2s_param[BT_SCO]	= {
+		.audio_port_id	= 3,
+		.is_i2s_master	= 1,
+		.i2s_mode	= TEGRA_DAIFMT_DSP_A,
+	},
+};
+
+static struct platform_device tegratab_audio_device = {
+	.name	= "tegra-snd-rt5640",
+	.id	= 0,
+	.dev	= {
+		.platform_data = &tegratab_audio_pdata,
+	},
+};
+
+static struct platform_device *tegratab_devices[] __initdata = {
+	&tegra_pmu_device,
+	&tegra_rtc_device,
+	&tegra_udc_device,
+#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
+	&tegra_smmu_device,
+#endif
+#if defined(CONFIG_TEGRA_AVP)
+	&tegra_avp_device,
+#endif
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
+	&tegra11_se_device,
+#endif
+	&tegra_ahub_device,
+	&tegra_dam_device0,
+	&tegra_dam_device1,
+	&tegra_dam_device2,
+	&tegra_i2s_device1,
+	&tegra_i2s_device3,
+	&tegra_i2s_device4,
+	&tegra_spdif_device,
+	&spdif_dit_device,
+	&bluetooth_dit_device,
+	&tegra_pcm_device,
+	&tegratab_audio_device,
+	&tegra_hda_device,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+	&tegra_aes_device,
+#endif
+};
+
+#ifdef CONFIG_USB_SUPPORT
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+	.port_otg = true,
+	.has_hostpc = true,
+	.support_pmu_vbus = true,
+	.phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+	.op_mode = TEGRA_USB_OPMODE_DEVICE,
+	.u_data.dev = {
+		.vbus_pmu_irq = 0,
+		.vbus_gpio = -1,
+		.charging_supported = false,
+		.remote_wakeup_supported = false,
+	},
+	.u_cfg.utmi = {
+		.hssync_start_delay = 0,
+		.elastic_limit = 16,
+		.idle_wait_delay = 17,
+		.term_range_adj = 6,
+		.xcvr_setup = 8,
+		.xcvr_lsfslew = 2,
+		.xcvr_lsrslew = 2,
+		.xcvr_setup_offset = 0,
+		.xcvr_use_fuses = 1,
+	},
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+	.port_otg = true,
+	.has_hostpc = true,
+	.support_pmu_vbus = true,
+	.unaligned_dma_buf_supported = false,
+	.phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+	.op_mode = TEGRA_USB_OPMODE_HOST,
+	.u_data.host = {
+		.vbus_gpio = -1,
+		.hot_plug = false,
+		.remote_wakeup_supported = true,
+		.power_off_on_suspend = true,
+	},
+	.u_cfg.utmi = {
+		.hssync_start_delay = 0,
+		.elastic_limit = 16,
+		.idle_wait_delay = 17,
+		.term_range_adj = 6,
+		.xcvr_setup = 15,
+		.xcvr_lsfslew = 2,
+		.xcvr_lsrslew = 2,
+		.xcvr_setup_offset = 0,
+		.xcvr_use_fuses = 1,
+		.vbus_oc_map = 0x4,
+	},
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+	.ehci_device = &tegra_ehci1_device,
+	.ehci_pdata = &tegra_ehci1_utmi_pdata,
+	.extcon_dev_name = "palmas-extcon",
+};
+
+static void tegratab_usb_init(void)
+{
+	int usb_port_owner_info = tegra_get_usb_port_owner_info();
+
+	/* Set USB wake sources for tegratab */
+	tegra_set_usb_wake_source();
+
+	if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
+		if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11 &&
+			tegra_revision == TEGRA_REVISION_A02) {
+			tegra_ehci1_utmi_pdata \
+			.unaligned_dma_buf_supported = true;
+			tegra_udc_pdata.unaligned_dma_buf_supported = true;
+		}
+		tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+		platform_device_register(&tegra_otg_device);
+		/* Setup the udc platform data */
+		tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+	}
+}
+
+static struct gpio modem_gpios[] = { /* Nemo modem */
+	{MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
+	{MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
+	.port_otg = false,
+	.has_hostpc = true,
+	.unaligned_dma_buf_supported = false,
+	.phy_intf = TEGRA_USB_PHY_INTF_HSIC,
+	.op_mode = TEGRA_USB_OPMODE_HOST,
+	.u_data.host = {
+		.vbus_gpio = -1,
+		.hot_plug = false,
+		.remote_wakeup_supported = true,
+		.power_off_on_suspend = true,
+	},
+};
+
+static int baseband_init(void)
+{
+	int ret;
+
+	ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
+	if (ret) {
+		pr_warn("%s:gpio request failed\n", __func__);
+		return ret;
+	}
+
+	/* enable pull-down for MDM_COLD_BOOT */
+	tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
+				    TEGRA_PUPD_PULL_DOWN);
+
+	/* export GPIO for user space access through sysfs */
+	gpio_export(MDM_RST, false);
+
+	return 0;
+}
+
+static const struct tegra_modem_operations baseband_operations = {
+	.init = baseband_init,
+};
+
+static struct tegra_usb_modem_power_platform_data baseband_pdata = {
+	.ops = &baseband_operations,
+	.wake_gpio = -1,
+	.boot_gpio = MDM_COLDBOOT,
+	.boot_irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+	.autosuspend_delay = 2000,
+	.short_autosuspend_delay = 50,
+	.tegra_ehci_device = &tegra_ehci2_device,
+	.tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
+};
+
+static struct platform_device icera_nemo_device = {
+	.name = "tegra_usb_modem_power",
+	.id = -1,
+	.dev = {
+		.platform_data = &baseband_pdata,
+	},
+};
+
+static void tegratab_modem_init(void)
+{
+	int modem_id = tegra_get_modem_id();
+	int usb_port_owner_info = tegra_get_usb_port_owner_info();
+	switch (modem_id) {
+	case TEGRA_BB_NEMO: /* on board i500 HSIC */
+		if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
+			if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA11) &&
+				(tegra_revision == TEGRA_REVISION_A02))
+				tegra_ehci2_hsic_baseband_pdata \
+				.unaligned_dma_buf_supported = true;
+			platform_device_register(&icera_nemo_device);
+		}
+		break;
+	}
+}
+
+#else
+static void tegratab_usb_init(void) { }
+static void tegratab_modem_init(void) { }
+#endif
+
+static void tegratab_audio_init(void)
+{
+	struct board_info board_info;
+
+	tegra_get_board_info(&board_info);
+
+	tegratab_audio_pdata.codec_name = "rt5640.0-001c";
+	tegratab_audio_pdata.codec_dai_name = "rt5640-aif1";
+}
+
+
+static struct platform_device *tegratab_spi_devices[] __initdata = {
+	&tegra11_spi_device1,
+};
+
+struct spi_clk_parent spi_parent_clk_tegratab[] = {
+	[0] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+	[1] = {.name = "pll_m"},
+	[2] = {.name = "clk_m"},
+#else
+	[1] = {.name = "clk_m"},
+#endif
+};
+
+static struct tegra_spi_platform_data tegratab_spi_pdata = {
+	.max_dma_buffer         = 16 * 1024,
+	.is_clkon_always        = false,
+	.max_rate               = 25000000,
+};
+
+static void __init tegratab_spi_init(void)
+{
+	int i;
+	struct clk *c;
+	struct board_info board_info, display_board_info;
+
+	tegra_get_board_info(&board_info);
+	tegra_get_display_board_info(&display_board_info);
+
+	for (i = 0; i < ARRAY_SIZE(spi_parent_clk_tegratab); ++i) {
+		c = tegra_get_clock_by_name(spi_parent_clk_tegratab[i].name);
+		if (IS_ERR_OR_NULL(c)) {
+			pr_err("Not able to get the clock for %s\n",
+					spi_parent_clk_tegratab[i].name);
+			continue;
+		}
+		spi_parent_clk_tegratab[i].parent_clk = c;
+		spi_parent_clk_tegratab[i].fixed_clk_rate = clk_get_rate(c);
+	}
+	tegratab_spi_pdata.parent_clk_list = spi_parent_clk_tegratab;
+	tegratab_spi_pdata.parent_clk_count =
+		ARRAY_SIZE(spi_parent_clk_tegratab);
+	tegratab_spi_pdata.is_dma_based =
+		(tegra_revision == TEGRA_REVISION_A01) ? false : true;
+	tegra11_spi_device1.dev.platform_data = &tegratab_spi_pdata;
+	platform_add_devices(tegratab_spi_devices,
+		ARRAY_SIZE(tegratab_spi_devices));
+}
+
+static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
+	/* name         parent          rate            enabled */
+	{ "extern2",    "pll_p",        41000000,       false},
+	{ "clk_out_2",  "extern2",      40800000,       false},
+	{ NULL,         NULL,           0,              0},
+};
+
+struct rm_spi_ts_platform_data rm31080ts_tegratab_data = {
+	.gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
+	.config = 0,
+	.platform_id = RM_PLATFORM_D010,
+	.name_of_clock = "clk_out_2",
+	.name_of_clock_con = "extern2",
+};
+
+static struct tegra_spi_device_controller_data dev_cdata = {
+	.rx_clk_tap_delay = 0,
+	.tx_clk_tap_delay = 16,
+};
+
+struct spi_board_info rm31080a_tegratab_spi_board[1] = {
+	{
+	 .modalias = "rm_ts_spidev",
+	 .bus_num = 0,
+	 .chip_select = 0,
+	 .max_speed_hz = 12 * 1000 * 1000,
+	 .mode = SPI_MODE_0,
+	 .controller_data = &dev_cdata,
+	 .platform_data = &rm31080ts_tegratab_data,
+	 },
+};
+
+static int __init tegratab_touch_init(void)
+{
+	struct board_info board_info;
+
+	tegra_get_display_board_info(&board_info);
+	tegra_clk_init_from_table(touch_clk_init_table);
+	rm31080ts_tegratab_data.platform_id = RM_PLATFORM_D010;
+	mdelay(20);
+	rm31080a_tegratab_spi_board[0].irq =
+		gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
+	touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
+				TOUCH_GPIO_RST_RAYDIUM_SPI,
+				&rm31080ts_tegratab_data,
+				&rm31080a_tegratab_spi_board[0],
+				ARRAY_SIZE(rm31080a_tegratab_spi_board));
+	return 0;
+}
+
+static void __init tegra_tegratab_init(void)
+{
+	struct board_info board_info;
+
+	tegra_get_display_board_info(&board_info);
+	tegra_clk_init_from_table(tegratab_clk_init_table);
+	tegra_clk_verify_parents();
+	tegra_soc_device_init("tegratab");
+	tegra_enable_pinmux();
+	tegratab_pinmux_init();
+	tegratab_i2c_init();
+	tegratab_spi_init();
+	tegratab_usb_init();
+	tegratab_uart_init();
+	tegratab_audio_init();
+	platform_add_devices(tegratab_devices, ARRAY_SIZE(tegratab_devices));
+	tegra_ram_console_debug_init();
+	tegra_io_dpd_init();
+	tegratab_regulator_init();
+	tegratab_sdhci_init();
+	tegratab_suspend_init();
+	tegratab_emc_init();
+	tegratab_edp_init();
+	tegratab_touch_init();
+	tegratab_panel_init();
+	tegratab_kbc_init();
+	tegratab_pmon_init();
+#if defined CONFIG_TI_ST || defined CONFIG_TI_ST_MODULE
+	tegratab_bt_st();
+	tegratab_tegra_setup_st_host_wake();
+#endif
+	tegra_release_bootloader_fb();
+	tegratab_modem_init();
+#ifdef CONFIG_TEGRA_WDT_RECOVERY
+	tegra_wdt_recovery_init();
+#endif
+	tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
+	tegratab_sensors_init();
+	tegratab_soctherm_init();
+	tegra_register_fuse();
+}
+
+static void __init tegratab_ramconsole_reserve(unsigned long size)
+{
+	tegra_ram_console_debug_reserve(SZ_1M);
+}
+
+static void __init tegra_tegratab_dt_init(void)
+{
+#ifdef CONFIG_USE_OF
+	of_platform_populate(NULL,
+		of_default_bus_match_table, NULL, NULL);
+#endif
+
+	tegra_tegratab_init();
+}
+
+static void __init tegra_tegratab_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+	/* 1920*1200*4*2 = 18432000 bytes */
+	tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
+#else
+	tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
+#endif
+	tegratab_ramconsole_reserve(SZ_1M);
+}
+
+static const char * const tegratab_dt_board_compat[] = {
+	"nvidia,tegratab",
+	NULL
+};
+
+MACHINE_START(TEGRATAB, "tegratab")
+	.atag_offset	= 0x100,
+	.soc		= &tegra_soc_desc,
+	.map_io		= tegra_map_common_io,
+	.reserve	= tegra_tegratab_reserve,
+	.init_early	= tegra11x_init_early,
+	.init_irq	= tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
+	.timer		= &tegra_timer,
+	.init_machine	= tegra_tegratab_dt_init,
+	.restart	= tegra_assert_system_reset,
+	.dt_compat	= tegratab_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-tegratab.h b/arch/arm/mach-tegra/board-tegratab.h
new file mode 100644
index 000000000000..3694cc9428ae
--- /dev/null
+++ b/arch/arm/mach-tegra/board-tegratab.h
@@ -0,0 +1,116 @@
+/*
+ * arch/arm/mach-tegra/board-tegratab.h
+ *
+ * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_BOARD_TEGRATAB_H
+#define _MACH_TEGRA_BOARD_TEGRATAB_H
+
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include "gpio-names.h"
+
+#define PMC_WAKE_STATUS 0x14
+#define PMC_WAKE2_STATUS 0x168
+
+/* External peripheral act as gpio */
+#define PALMAS_TEGRA_GPIO_BASE	TEGRA_NR_GPIOS
+
+/* Audio-related GPIOs */
+#define TEGRA_GPIO_CDC_IRQ		TEGRA_GPIO_PW3
+#define TEGRA_GPIO_LDO1_EN		TEGRA_GPIO_PV3
+#define TEGRA_GPIO_CODEC1_EN	TEGRA_GPIO_PP3
+#define TEGRA_GPIO_CODEC2_EN	TEGRA_GPIO_PP1
+#define TEGRA_GPIO_CODEC3_EN	TEGRA_GPIO_PV0
+
+#define TEGRA_GPIO_SPKR_EN		-1
+#define TEGRA_GPIO_HP_DET		TEGRA_GPIO_PR7
+#define TEGRA_GPIO_INT_MIC_EN		TEGRA_GPIO_PK3
+#define TEGRA_GPIO_EXT_MIC_EN		-1
+
+/* External peripheral act as interrupt controller */
+#define PALMAS_TEGRA_IRQ_BASE   TEGRA_NR_IRQS
+#define PALMAS_TEGRA_IRQ_END	(PALMAS_TEGRA_IRQ_BASE + PALMAS_NUM_IRQ)
+
+/* I2C related GPIOs */
+#define TEGRA_GPIO_I2C1_SCL		TEGRA_GPIO_PC4
+#define TEGRA_GPIO_I2C1_SDA             TEGRA_GPIO_PC5
+#define TEGRA_GPIO_I2C2_SCL             TEGRA_GPIO_PT5
+#define TEGRA_GPIO_I2C2_SDA             TEGRA_GPIO_PT6
+#define TEGRA_GPIO_I2C3_SCL             TEGRA_GPIO_PBB1
+#define TEGRA_GPIO_I2C3_SDA             TEGRA_GPIO_PBB2
+#define TEGRA_GPIO_I2C4_SCL             TEGRA_GPIO_PV4
+#define TEGRA_GPIO_I2C4_SDA             TEGRA_GPIO_PV5
+#define TEGRA_GPIO_I2C5_SCL             TEGRA_GPIO_PZ6
+#define TEGRA_GPIO_I2C5_SDA             TEGRA_GPIO_PZ7
+
+/* Camera related GPIOs */
+#define CAM_RSTN			TEGRA_GPIO_PBB3
+#define CAM_FLASH_STROBE		TEGRA_GPIO_PBB4
+#define CAM1_POWER_DWN_GPIO		TEGRA_GPIO_PBB5
+#define CAM2_POWER_DWN_GPIO		TEGRA_GPIO_PBB6
+#define CAM_AF_PWDN			TEGRA_GPIO_PBB7
+#define CAM_GPIO1			TEGRA_GPIO_PCC1
+#define CAM_GPIO2			TEGRA_GPIO_PCC2
+
+/* Touchscreen definitions */
+#define TOUCH_GPIO_IRQ_RAYDIUM_SPI      TEGRA_GPIO_PK2
+#define TOUCH_GPIO_RST_RAYDIUM_SPI      TEGRA_GPIO_PK4
+
+/* Invensense MPU Definitions */
+#define MPU_GYRO_NAME           "mpu6050"
+#define MPU_GYRO_IRQ_GPIO       TEGRA_GPIO_PR3
+#define MPU_GYRO_ADDR           0x69
+#define MPU_GYRO_BUS_NUM        0
+#define MPU_GYRO_ORIENTATION    { 0, 1, 0, -1, 0, 0, 0, 0, 1 }
+#define MPU_COMPASS_NAME        "ak8975"
+#define MPU_COMPASS_IRQ_GPIO    0
+#define MPU_COMPASS_ADDR        0x0D
+#define MPU_COMPASS_BUS_NUM     0
+#define MPU_COMPASS_ORIENTATION { 0, 1, 0, -1, 0, 0, 0, 0, 1 }
+
+/* Modem related GPIOs */
+#define MODEM_EN		TEGRA_GPIO_PP2
+#define MDM_RST			TEGRA_GPIO_PP0
+#define MDM_COLDBOOT		TEGRA_GPIO_PO5
+
+int tegratab_regulator_init(void);
+int tegratab_suspend_init(void);
+int tegratab_sdhci_init(void);
+int tegratab_pinmux_init(void);
+int tegratab_sensors_init(void);
+int tegratab_emc_init(void);
+int tegratab_edp_init(void);
+int tegratab_panel_init(void);
+int roth_panel_init(void);
+int tegratab_kbc_init(void);
+int tegratab_pmon_init(void);
+int tegratab_soctherm_init(void);
+
+/* UART port which is used by bluetooth*/
+#define BLUETOOTH_UART_DEV_NAME "/dev/ttyHS2"
+
+/* Baseband IDs */
+enum tegra_bb_type {
+	TEGRA_BB_NEMO = 1,
+};
+
+#define UTMI1_PORT_OWNER_XUSB	0x1
+#define UTMI2_PORT_OWNER_XUSB	0x2
+#define HSIC1_PORT_OWNER_XUSB	0x4
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra-board-id.h b/arch/arm/mach-tegra/tegra-board-id.h
index 2bcfba5f2d4e..aae067b036b0 100644
--- a/arch/arm/mach-tegra/tegra-board-id.h
+++ b/arch/arm/mach-tegra/tegra-board-id.h
@@ -1,7 +1,7 @@
 /*
  * tegra-board-id.h: Defines all boardid of Tegra.
  *
- * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,6 +33,7 @@
 #define BOARD_P2454   0x0996
 #define BOARD_E1582   0x062E
 #define BOARD_E1545   0x0609
+#define BOARD_E1569   0x0621
 
 /* Board Fab version */
 #define BOARD_FAB_A00			0x0
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 444a36d70b4d..050fee784e45 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1178,3 +1178,4 @@ tegra_pluto		MACH_TEGRA_PLUTO	TEGRA_PLUTO		4306
 tai			MACH_TAI		TAI			4311
 roth			MACH_ROTH		ROTH			4377
 macallan		MACH_MACALLAN		MACALLAN		4406
+tegratab		MACH_TEGRATAB		TEGRATAB		4544