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authorSandor Yu <R01008@freescale.com>2012-04-07 16:34:15 +0800
committerSandor Yu <R01008@freescale.com>2012-04-07 17:12:16 +0800
commit3ec8c998827be5729ff98a0d7c097f7ad9ddbc6e (patch)
treef616828a0ffc12cc8b25c04055bd52e108c97f3d
parent6b1f2e1be233b00c73e8f82feb1b397f0b62bc02 (diff)
ENGR00179130 Setting 480p Hsync and Vsync polarity is incorrect
Fix IPU DI registr DI_GENERAL incorrect initialize. Signed-off-by: Sandor Yu <R01008@freescale.com>
-rw-r--r--drivers/mxc/ipu3/ipu_disp.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
index a34d0601f2bf..229545c9cb34 100644
--- a/drivers/mxc/ipu3/ipu_disp.c
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -1292,8 +1292,8 @@ int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
/*clear DI*/
di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
- ipu_di_write(ipu, disp,
- di_gen & (0x3 << 20), DI_GENERAL);
+ di_gen &= (0x3 << 20);
+ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
if (sig.interlaced) {
if (g_ipu_hw_rev >= 2) {