diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2010-06-26 16:36:01 +0530 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-07-02 07:18:14 -0700 |
| commit | 4131b3d36a39f4661811fdcae8d7de20edbf34dc (patch) | |
| tree | b500ec0a5546a0ba18261d093f96801e5becaf1f | |
| parent | 171da4c9fd3a551598844cb6850e1017a917d392 (diff) | |
[arm/tegra] dma: Setting burst size to 4 words for i2s.
Setting the dma burst size to 4 words for the i2s client.
This will be default for i2s client. For othe client, the
burst size will remain unchanged.
Change-Id: I22610535910c1ba4e382da4deda29945be62003f
Reviewed-on: http://git-master.nvidia.com/r/3242
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/dma.c | 43 |
1 files changed, 30 insertions, 13 deletions
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c index c4010867dd00..2838f0a418b8 100644 --- a/arch/arm/mach-tegra/dma.c +++ b/arch/arm/mach-tegra/dma.c @@ -424,6 +424,35 @@ static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch, return; } +static void set_burst_size(struct tegra_dma_channel *ch, + struct tegra_dma_req *req) +{ + ch->ahb_seq &= ~AHB_SEQ_BURST_MASK; + switch(req->req_sel) { + case TEGRA_DMA_REQ_SEL_SL2B1: + case TEGRA_DMA_REQ_SEL_SL2B2: + case TEGRA_DMA_REQ_SEL_SL2B3: + case TEGRA_DMA_REQ_SEL_SL2B4: + case TEGRA_DMA_REQ_SEL_SPI: + /* For spi/slink the burst size based on transfer size + * i.e. if multiple of 16 bytes then busrt is + * 4 word else burst size is 1 word */ + if (req->size & 0xF) + ch->ahb_seq |= AHB_SEQ_BURST_1; + else + ch->ahb_seq |= AHB_SEQ_BURST_4; + break; + case TEGRA_DMA_REQ_SEL_I2S_2: + case TEGRA_DMA_REQ_SEL_I2S_1: + case TEGRA_DMA_REQ_SEL_I2S2_2: + case TEGRA_DMA_REQ_SEL_I2S2_1: + ch->ahb_seq |= AHB_SEQ_BURST_4; + break; + default: + ch->ahb_seq |= AHB_SEQ_BURST_1; + break; + } +} static void tegra_dma_update_hw(struct tegra_dma_channel *ch, struct tegra_dma_req *req) { @@ -437,20 +466,8 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch, ch->csr |= CSR_FLOW; ch->csr &= ~CSR_REQ_SEL_MASK; ch->csr |= req->req_sel << CSR_REQ_SEL_SHIFT; - ch->ahb_seq &= ~AHB_SEQ_BURST_MASK; - /* If slink is the requestor then set burst size based on - * transfer size i.e. if multiple of 16 bytes then busrt is - * 4 word else burst size is 1 word */ - if ((TEGRA_DMA_REQ_SEL_SL2B1 <= req->req_sel) && - (req->req_sel <= TEGRA_DMA_REQ_SEL_SL2B4)) { - if (req->size & 0xF) - ch->ahb_seq |= AHB_SEQ_BURST_1; - else - ch->ahb_seq |= AHB_SEQ_BURST_4; - } else { - ch->ahb_seq |= AHB_SEQ_BURST_1; - } + set_burst_size(ch, req); /* One shot mode is always single buffered, * continuous mode is always double buffered |