Merge branch 'pinctrl/next' into next

* pinctrl/next: (18 commits)
  pinctrl: s32v234: Add FlexCAN pins to S32V234 driver
  dt-bindings: pinctrl: s32v234: Add defines for all pins
  dt-bindings: pinctrl: s32v234: Add macros for MSCR and config pairs
  pinctrl: s32v234: Remove s32v234_pins enum
  dt-bindings: pinctrl: s32v234: Add macros for MSCR/IMCR numbers
  ...

12 files changed, 2128 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt b/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt
new file mode 100644
index 000000000000..676357664a8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt
@@ -0,0 +1,19 @@
+* Freescale SIUL2 iomux controller
+
+See chapter 20 ("System Integration Unit Lite2 (SIUL2)") in the reference
+manual[1].
+
+Based on fsl,imx-pincontrol implementation.
+
+Required properties:
+- compatible: "fsl,s32v234-siul2"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>
+  PIN_FUNC_ID - id of MSCR to be modified
+  CONFIG - configuration to be written in the MSCR/IMCR register
+
+  Even though IMCR register should be used as input register, it can be
+  set and addressed in the same way as MSCR, only instead of passing the
+  IMCR index, IMCR_IDX + 512 is passed[1].
+
+[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index fcd37e93ed4d..c42d8c241ad5 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -71,6 +71,13 @@ pinctrl-names:	The list of names to assign states. List entry 0 defines the
 		name for integer state ID 0, list entry 1 for state ID 1, and
 		so on.
 
+pinctrl-assert-gpios:
+		List of phandles, each pointing at a GPIO which is used by some
+		board design to steer pins between two peripherals on the board.
+		It plays like a board level pin multiplexer to choose different
+		functions for given pins by pulling up/down the GPIOs.  See
+		bindings/gpio/gpio.txt for details of how to specify GPIO.
+
 For example:
 
 	/* For a client device requiring named states */
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index b4a5a4de80ee..5785677c9b31 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -221,9 +221,17 @@ config ARCH_ROCKCHIP
 config ARCH_S32
 	bool "NXP S32 SoC Family"
 	select ARCH_S32_CLK
+	select PINCTRL
 	help
 	  This enables support for the NXP S32 family of processors.
 
+if ARCH_S32
+menu "S32 SOC selection"
+	config SOC_S32V234
+		bool "S32V234 SOC"
+endmenu
+endif
+
 config ARCH_SEATTLE
 	bool "AMD Seattle SoC Family"
 	help
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index 5d6d8b1e9062..a2d7910c5188 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -7,6 +7,7 @@
 
 #include <linux/device.h>
 #include <linux/of.h>
+#include <linux/of_gpio.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/slab.h>
 
@@ -181,6 +182,46 @@ bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev)
 	return prop ? true : false;
 }
 
+static int dt_gpio_assert_pinctrl(struct pinctrl *p)
+{
+	struct device_node *np = p->dev->of_node;
+	enum of_gpio_flags flags;
+	int gpio;
+	int index = 0;
+	int ret;
+
+	if (!of_find_property(np, "pinctrl-assert-gpios", NULL))
+		return 0; /* Missing the property, so nothing to be done */
+
+	for (;; index++) {
+		gpio = of_get_named_gpio_flags(np, "pinctrl-assert-gpios",
+					       index, &flags);
+		if (gpio < 0) {
+			if (gpio == -EPROBE_DEFER)
+				return gpio;
+			break; /* End of the phandle list */
+		}
+
+		if (!gpio_is_valid(gpio))
+			return -EINVAL;
+
+		ret = devm_gpio_request_one(p->dev, gpio, GPIOF_OUT_INIT_LOW,
+					    NULL);
+		if (ret < 0)
+			return ret;
+
+		if (flags & OF_GPIO_ACTIVE_LOW)
+			continue;
+
+		if (gpio_cansleep(gpio))
+			gpio_set_value_cansleep(gpio, 1);
+		else
+			gpio_set_value(gpio, 1);
+	}
+
+	return 0;
+}
+
 int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev)
 {
 	struct device_node *np = p->dev->of_node;
@@ -201,6 +242,12 @@ int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev)
 		return 0;
 	}
 
+	ret = dt_gpio_assert_pinctrl(p);
+	if (ret) {
+		dev_dbg(p->dev, "failed to assert pinctrl setting: %d\n", ret);
+		return ret;
+	}
+
 	/* We may store pointers to property names within the node */
 	of_node_get(np);
 
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 5f4058033ec6..01bc57662ac3 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -177,3 +177,16 @@ config PINCTRL_IMX23
 config PINCTRL_IMX28
 	bool
 	select PINCTRL_MXS
+
+config PINCTRL_S32V_CORE
+	bool "Core driver for the S32V pin controller"
+	help
+	  Say Y here to enable the S32V pin controller
+
+config PINCTRL_S32V234
+	bool "Freescale S32V234 pinctrl driver"
+	depends on SOC_S32V234
+	select PINCTRL_IMX
+	select PINCTRL_S32V_CORE
+	help
+	  Say Y here to enable the Freescale S32V234 pinctrl driver
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 78e9140c13e3..5ec6e6f9f959 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -28,3 +28,5 @@ obj-$(CONFIG_PINCTRL_MXS)	+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o
 obj-$(CONFIG_PINCTRL_IMX25)	+= pinctrl-imx25.o
 obj-$(CONFIG_PINCTRL_IMX28)	+= pinctrl-imx28.o
+obj-$(CONFIG_PINCTRL_S32V234)	+= pinctrl-s32v234.o
+obj-$(CONFIG_PINCTRL_S32V_CORE)	+= pinctrl-s32v-core.o
diff --git a/drivers/pinctrl/freescale/pinctrl-s32v-core.c b/drivers/pinctrl/freescale/pinctrl-s32v-core.c
new file mode 100644
index 000000000000..75d0adc2be25
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-s32v-core.c
@@ -0,0 +1,526 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Core driver for the S32V pin controller
+ *
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * Based on pinctrl-imx.c:
+ *	Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *	Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *	Copyright (C) 2012 Linaro Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "pinctrl-s32v.h"
+
+/**
+ * @dev: a pointer back to containing device
+ * @base: the offset to the controller in virtual memory
+ */
+struct s32v_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pctl;
+	void __iomem *base;
+	const struct s32v_pinctrl_soc_info *info;
+};
+
+static const char *pin_get_name_from_info(struct s32v_pinctrl_soc_info *info,
+					  const unsigned int pin_id)
+{
+	int i;
+
+	for (i = 0; i < info->npins; i++) {
+		if (info->pins[i].number == pin_id)
+			return info->pins[i].name;
+	}
+
+	return NULL;
+}
+
+static inline const struct s32v_pin_group *s32v_pinctrl_find_group_by_name(
+				const struct s32v_pinctrl_soc_info *info,
+				const char *name)
+{
+	const struct s32v_pin_group *grp = NULL;
+	unsigned int i;
+
+	for (i = 0; i < info->ngroups; i++) {
+		if (!strcmp(info->groups[i].name, name)) {
+			grp = &info->groups[i];
+			break;
+		}
+	}
+
+	return grp;
+}
+
+static int s32v_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+
+	return info->ngroups;
+}
+
+static const char *s32v_get_group_name(struct pinctrl_dev *pctldev,
+				       unsigned int selector)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+
+	return info->groups[selector].name;
+}
+
+static int s32v_get_group_pins(struct pinctrl_dev *pctldev,
+			       unsigned int selector, const unsigned int **pins,
+			       unsigned int *npins)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+
+	if (selector >= info->ngroups)
+		return -EINVAL;
+
+	*pins = info->groups[selector].pin_ids;
+	*npins = info->groups[selector].npins;
+
+	return 0;
+}
+
+static void s32v_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+			      unsigned int offset)
+{
+	seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int s32v_dt_node_to_map(struct pinctrl_dev *pctldev,
+			       struct device_node *np,
+			       struct pinctrl_map **map, unsigned int *num_maps)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+	const struct s32v_pin_group *grp;
+	struct pinctrl_map *new_map;
+	struct device_node *parent;
+	int map_num = 1;
+	int i, j;
+
+	/*
+	 * first find the group of this node and check if we need create
+	 * config maps for pins
+	 */
+	grp = s32v_pinctrl_find_group_by_name(info, np->name);
+	if (!grp) {
+		dev_err(info->dev, "unable to find group for node %s\n",
+			np->name);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < grp->npins; i++)
+		map_num++;
+
+	new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
+				GFP_KERNEL);
+	if (!new_map)
+		return -ENOMEM;
+
+	*map = new_map;
+	*num_maps = map_num;
+
+	/* create mux map */
+	parent = of_get_parent(np);
+	if (!parent) {
+		kfree(new_map);
+		return -EINVAL;
+	}
+	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+	new_map[0].data.mux.function = parent->name;
+	new_map[0].data.mux.group = np->name;
+	of_node_put(parent);
+
+	/* create config map */
+	new_map++;
+	for (i = j = 0; i < grp->npins; i++) {
+		new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+		new_map[j].data.configs.group_or_pin =
+			pin_get_name(pctldev, grp->pins[i].pin_id);
+		new_map[j].data.configs.configs = &grp->pins[i].config;
+		new_map[j].data.configs.num_configs = 1;
+		j++;
+	}
+
+	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+	return 0;
+}
+
+static void s32v_dt_free_map(struct pinctrl_dev *pctldev,
+			     struct pinctrl_map *map, unsigned int num_maps)
+{
+	kfree(map);
+}
+
+static const struct pinctrl_ops s32v_pctrl_ops = {
+	.get_groups_count = s32v_get_groups_count,
+	.get_group_name = s32v_get_group_name,
+	.get_group_pins = s32v_get_group_pins,
+	.pin_dbg_show = s32v_pin_dbg_show,
+	.dt_node_to_map = s32v_dt_node_to_map,
+	.dt_free_map = s32v_dt_free_map,
+
+};
+
+static int s32v_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector,
+			unsigned int group)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+	unsigned int npins, pin_id;
+	int i;
+	struct s32v_pin_group *grp;
+
+	/*
+	 * Configure the mux mode for each pin in the group for a specific
+	 * function.
+	 */
+	grp = &info->groups[group];
+	npins = grp->npins;
+
+	dev_dbg(ipctl->dev, "enable function %s group %s\n",
+		info->functions[selector].name, grp->name);
+
+	for (i = 0; i < npins; i++) {
+		struct s32v_pin *pin = &grp->pins[i];
+
+		pin_id = pin->pin_id;
+
+		writel(pin->config, ipctl->base + S32V_PAD_CONFIG(pin_id));
+		dev_dbg(ipctl->dev, "write: offset 0x%x val %lu\n",
+			S32V_PAD_CONFIG(pin_id), pin->config);
+	}
+
+	return 0;
+}
+
+static int s32v_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+
+	return info->nfunctions;
+}
+
+static const char *s32v_pmx_get_func_name(struct pinctrl_dev *pctldev,
+					  unsigned int selector)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+
+	return info->functions[selector].name;
+}
+
+static int s32v_pmx_get_groups(struct pinctrl_dev *pctldev,
+			       unsigned int selector,
+			       const char * const **groups,
+			       unsigned int * const num_groups)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+
+	*groups = info->functions[selector].groups;
+	*num_groups = info->functions[selector].num_groups;
+
+	return 0;
+}
+
+static const struct pinmux_ops s32v_pmx_ops = {
+	.get_functions_count = s32v_pmx_get_funcs_count,
+	.get_function_name = s32v_pmx_get_func_name,
+	.get_function_groups = s32v_pmx_get_groups,
+	.set_mux = s32v_pmx_set,
+};
+
+static int s32v_pinconf_get(struct pinctrl_dev *pctldev,
+			    unsigned int pin_id, unsigned long *config)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+	*config = readl(ipctl->base + S32V_PAD_CONFIG(pin_id));
+
+	return 0;
+}
+
+static int s32v_pinconf_set(struct pinctrl_dev *pctldev,
+			    unsigned int pin_id, unsigned long *configs,
+			    unsigned int num_configs)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	int i;
+
+	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
+		pin_get_name(pctldev, pin_id));
+
+	for (i = 0; i < num_configs; i++) {
+		writel(configs[i], ipctl->base + S32V_PAD_CONFIG(pin_id));
+		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+			S32V_PAD_CONFIG(pin_id), configs[i]);
+	} /* for each config */
+
+	return 0;
+}
+
+static void s32v_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+				  struct seq_file *s, unsigned int pin_id)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	unsigned long config;
+
+	config = readl(ipctl->base + S32V_PAD_CONFIG(pin_id));
+	seq_printf(s, "0x%lx", config);
+}
+
+static void s32v_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+					struct seq_file *s, unsigned int group)
+{
+	struct s32v_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct s32v_pinctrl_soc_info *info = ipctl->info;
+	struct s32v_pin_group *grp;
+	unsigned long config;
+	const char *name;
+	int i, ret;
+
+	if (group > info->ngroups)
+		return;
+
+	seq_puts(s, "\n");
+	grp = &info->groups[group];
+	for (i = 0; i < grp->npins; i++) {
+		struct s32v_pin *pin = &grp->pins[i];
+
+		name = pin_get_name(pctldev, pin->pin_id);
+		ret = s32v_pinconf_get(pctldev, pin->pin_id, &config);
+		if (ret)
+			return;
+		seq_printf(s, "%s: 0x%lx", name, config);
+	}
+}
+
+static const struct pinconf_ops s32v_pinconf_ops = {
+	.pin_config_get = s32v_pinconf_get,
+	.pin_config_set = s32v_pinconf_set,
+	.pin_config_dbg_show = s32v_pinconf_dbg_show,
+	.pin_config_group_dbg_show = s32v_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc s32v_pinctrl_desc = {
+	.pctlops = &s32v_pctrl_ops,
+	.pmxops = &s32v_pmx_ops,
+	.confops = &s32v_pinconf_ops,
+	.owner = THIS_MODULE,
+};
+
+/*
+ * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
+ * 1 u32 CONFIG, so 24 types in total for each pin.
+ */
+#define FSL_PIN_SIZE 24
+#define SHARE_FSL_PIN_SIZE 20
+
+static int s32v_pinctrl_parse_groups(struct device_node *np,
+				     struct s32v_pin_group *grp,
+				     struct s32v_pinctrl_soc_info *info,
+				     u32 index)
+{
+	int size, i;
+	const __be32 *list;
+
+	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+	/* Initialise group */
+	grp->name = np->name;
+
+	/*
+	 * the binding format is fsl,pins = <PIN CONFIG>,
+	 * do sanity check and calculate pins number
+	 */
+	list = of_get_property(np, "fsl,pins", &size);
+	if (!list) {
+		dev_err(info->dev, "no fsl,pins property in node %s\n",
+			np->full_name);
+		return -EINVAL;
+	}
+
+	/* we do not check return since it's safe node passed down */
+	if (!size || size % S32V_PIN_SIZE) {
+		dev_err(info->dev, "Invalid fsl,pins property in node %s\n",
+			np->full_name);
+		return -EINVAL;
+	}
+
+	grp->npins = size / S32V_PIN_SIZE;
+	grp->pins = devm_kzalloc(info->dev,
+				 grp->npins * sizeof(struct s32v_pin),
+				 GFP_KERNEL);
+	grp->pin_ids = devm_kzalloc(info->dev,
+				    grp->npins * sizeof(unsigned int),
+				    GFP_KERNEL);
+	if (!grp->pins || !grp->pin_ids)
+		return -ENOMEM;
+
+	for (i = 0; i < grp->npins; i++) {
+		struct s32v_pin *pin = &grp->pins[i];
+
+		pin->pin_id = be32_to_cpu(*list++);
+		pin->config = be32_to_cpu(*list++);
+		grp->pin_ids[i] = grp->pins[i].pin_id;
+
+		dev_dbg(info->dev, "%s: 0x%08lx",
+			pin_get_name_from_info(info, pin->pin_id), pin->config);
+	}
+
+	return 0;
+}
+
+static int s32v_pinctrl_parse_functions(struct device_node *np,
+					struct s32v_pinctrl_soc_info *info,
+					u32 index)
+{
+	struct device_node *child;
+	struct s32v_pmx_func *func;
+	struct s32v_pin_group *grp;
+	static u32 grp_index;
+	u32 i = 0;
+
+	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+	func = &info->functions[index];
+
+	/* Initialise function */
+	func->name = np->name;
+	func->num_groups = of_get_child_count(np);
+	if (func->num_groups == 0) {
+		dev_err(info->dev, "no groups defined in %s\n", np->full_name);
+		return -EINVAL;
+	}
+	func->groups = devm_kzalloc(info->dev,
+				    func->num_groups * sizeof(char *),
+				    GFP_KERNEL);
+
+	for_each_child_of_node(np, child) {
+		func->groups[i] = child->name;
+		grp = &info->groups[grp_index++];
+		s32v_pinctrl_parse_groups(child, grp, info, i++);
+	}
+
+	return 0;
+}
+
+static int s32v_pinctrl_probe_dt(struct platform_device *pdev,
+				 struct s32v_pinctrl_soc_info *info)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *child;
+	u32 nfuncs = 0;
+	u32 i = 0;
+
+	if (!np)
+		return -ENODEV;
+
+	nfuncs = of_get_child_count(np);
+	if (nfuncs <= 0) {
+		dev_err(&pdev->dev, "no functions defined\n");
+		return -EINVAL;
+	}
+
+	info->nfunctions = nfuncs;
+	info->functions = devm_kzalloc(&pdev->dev,
+				       nfuncs * sizeof(struct s32v_pmx_func),
+				       GFP_KERNEL);
+	if (!info->functions)
+		return -ENOMEM;
+
+	info->ngroups = 0;
+	for_each_child_of_node(np, child)
+		info->ngroups += of_get_child_count(child);
+	info->groups = devm_kzalloc(&pdev->dev, info->ngroups *
+						sizeof(struct s32v_pin_group),
+				    GFP_KERNEL);
+	if (!info->groups)
+		return -ENOMEM;
+
+	for_each_child_of_node(np, child)
+		s32v_pinctrl_parse_functions(child, info, i++);
+
+	return 0;
+}
+
+int s32v_pinctrl_probe(struct platform_device *pdev,
+		       struct s32v_pinctrl_soc_info *info)
+{
+	struct s32v_pinctrl *ipctl;
+	struct resource *res;
+	int ret;
+
+	if (!info || !info->pins || !info->npins) {
+		dev_err(&pdev->dev, "wrong pinctrl info\n");
+		return -EINVAL;
+	}
+	info->dev = &pdev->dev;
+
+	/* Create state holders etc for this driver */
+	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+	if (!ipctl)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
+
+	if (IS_ERR(ipctl->base))
+		return PTR_ERR(ipctl->base);
+
+	s32v_pinctrl_desc.name = dev_name(&pdev->dev);
+	s32v_pinctrl_desc.pins = info->pins;
+	s32v_pinctrl_desc.npins = info->npins;
+
+	ret = s32v_pinctrl_probe_dt(pdev, info);
+	if (ret) {
+		dev_err(&pdev->dev, "fail to probe dt properties\n");
+		return ret;
+	}
+
+	ipctl->info = info;
+	ipctl->dev = info->dev;
+	platform_set_drvdata(pdev, ipctl);
+	ipctl->pctl = pinctrl_register(&s32v_pinctrl_desc, &pdev->dev, ipctl);
+	if (!ipctl->pctl) {
+		dev_err(&pdev->dev, "could not register s32 pinctrl driver\n");
+		return -EINVAL;
+	}
+
+	dev_info(&pdev->dev, "initialized s32 pinctrl driver\n");
+
+	return 0;
+}
+
+int s32v_pinctrl_remove(struct platform_device *pdev)
+{
+	struct s32v_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+	pinctrl_unregister(ipctl->pctl);
+
+	return 0;
+}
diff --git a/drivers/pinctrl/freescale/pinctrl-s32v.h b/drivers/pinctrl/freescale/pinctrl-s32v.h
new file mode 100644
index 000000000000..f231607bbc5b
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-s32v.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * S32V pinmux core definitions
+ *
+ * Copyright (C) 2017 NXP
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Based on pinctrl-imx.h, by Dong Aisheng <dong.aisheng@linaro.org>
+ */
+
+#ifndef __DRIVERS_PINCTRL_S32V_H
+#define __DRIVERS_PINCTRL_S32V_H
+
+struct platform_device;
+
+/**
+ * struct s32v_pin - describes a single S32V pin
+ * @pin_id: the pin_id of this pin
+ * @config: the config for this pin.
+ */
+struct s32v_pin {
+	unsigned int pin_id;
+	unsigned long config;
+};
+
+/**
+ * struct s32v_pin_group - describes an S32V pin group
+ * @name: the name of this specific pin group
+ * @npins: the number of pins in this group array, i.e. the number of
+ *	elements in .pins so we can iterate over that array
+ * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array
+ * @pins: array of pins
+ */
+struct s32v_pin_group {
+	const char *name;
+	unsigned int npins;
+	unsigned int *pin_ids;
+	struct s32v_pin *pins;
+};
+
+/**
+ * struct s32v_pmx_func - describes S32V pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct s32v_pmx_func {
+	const char *name;
+	const char **groups;
+	unsigned int num_groups;
+};
+
+struct s32v_pinctrl_soc_info {
+	struct device *dev;
+	const struct pinctrl_pin_desc *pins;
+	unsigned int npins;
+	struct s32v_pin_group *groups;
+	unsigned int ngroups;
+	struct s32v_pmx_func *functions;
+	unsigned int nfunctions;
+	unsigned int flags;
+};
+
+#define S32V_PINCTRL_PIN(pin)	PINCTRL_PIN(pin, #pin)
+#define S32V_PAD_CONFIG(idx)	(0x240 + (idx) * 4)
+#define S32V_PIN_SIZE		(8)
+
+int s32v_pinctrl_probe(struct platform_device *pdev,
+		       struct s32v_pinctrl_soc_info *info);
+int s32v_pinctrl_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_S32V_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-s32v234.c b/drivers/pinctrl/freescale/pinctrl-s32v234.c
new file mode 100644
index 000000000000..6c64f4cdcc8c
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-s32v234.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * s32v234 pinctrl driver based on imx pinmux and pinconf core
+ *
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017, 2019 NXP
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <dt-bindings/pinctrl/s32v234-pinctrl.h>
+
+#include "pinctrl-s32v.h"
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc s32v234_pinctrl_pads[] = {
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PA15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PB15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PC15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PD15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PE15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PF15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PG15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PH15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PJ15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK6),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK7),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK8),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK9),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK10),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK11),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK12),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK13),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK14),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PK15),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PL0),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PL1),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PL2),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PL3),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PL4),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PL5),
+	S32V_PINCTRL_PIN(S32V234_MSCR_PL8),
+
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_CLK),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_CMD),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT0),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT1),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT2),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT3),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT4),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT5),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT6),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_DAT7),
+	S32V_PINCTRL_PIN(S32V234_IMCR_CAN_FD0_RXD),
+	S32V_PINCTRL_PIN(S32V234_IMCR_CAN_FD1_RXD),
+	S32V_PINCTRL_PIN(S32V234_IMCR_UART0_RXD),
+	S32V_PINCTRL_PIN(S32V234_IMCR_UART1_RXD),
+	S32V_PINCTRL_PIN(S32V234_IMCR_USDHC_WP),
+
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_RX_ER),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_COL),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_CRS),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_RX_DV),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_RX_D0),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_RX_D1),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_RX_D2),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_RX_D3),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_TX_CLK),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_RX_CLK),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_MDIO),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_TIMER0),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_TIMER1),
+	S32V_PINCTRL_PIN(S32V234_IMCR_Ethernet_TIMER2),
+};
+
+static struct s32v_pinctrl_soc_info s32v234_pinctrl_info = {
+	.pins = s32v234_pinctrl_pads,
+	.npins = ARRAY_SIZE(s32v234_pinctrl_pads),
+};
+
+static const struct of_device_id s32v234_pinctrl_of_match[] = {
+	{ .compatible = "fsl,s32v234-siul2", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, s32v234_pinctrl_of_match);
+
+static int s32v234_pinctrl_probe(struct platform_device *pdev)
+{
+	return s32v_pinctrl_probe(pdev, &s32v234_pinctrl_info);
+}
+
+static struct platform_driver s32v234_pinctrl_driver = {
+	.driver = {
+		.name = "s32v234-siul2",
+		.owner = THIS_MODULE,
+		.of_match_table = s32v234_pinctrl_of_match,
+	},
+	.probe = s32v234_pinctrl_probe,
+	.remove = s32v_pinctrl_remove,
+};
+
+module_platform_driver(s32v234_pinctrl_driver);
+
+MODULE_DESCRIPTION("Freescale S32V234 pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
index bfe9ab7c684c..e4abcd6f787f 100644
--- a/include/dt-bindings/pinctrl/pads-imx8qxp.h
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -747,6 +747,7 @@
 #define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B                     IMX8QXP_QSPI0B_SS1_B                  1
 #define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3                        IMX8QXP_QSPI0B_SS1_B                  2
 #define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24                       IMX8QXP_QSPI0B_SS1_B                  4
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD                  IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
 
 /*!
  * @name Fake Pad Mux Definitions
diff --git a/include/dt-bindings/pinctrl/s32v234-pinctrl.h b/include/dt-bindings/pinctrl/s32v234-pinctrl.h
new file mode 100644
index 000000000000..8736d556a38c
--- /dev/null
+++ b/include/dt-bindings/pinctrl/s32v234-pinctrl.h
@@ -0,0 +1,1173 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2016 by Freescale Semiconductor
+ * Copyright 2016-2017, 2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_S32V234_PINCTRL_H__
+#define __DT_BINDINGS_S32V234_PINCTRL_H__
+
+/*
+ * Use to set PAD control
+ */
+#define PAD_CTL_DCYLE_TRIM_OFS      (22)
+#define PAD_CTL_DCYLE_TRIM_NONE     (0 << PAD_CTL_DCYLE_TRIM_OFS)
+#define PAD_CTL_DCYLE_TRIM_LEFT     (1 << PAD_CTL_DCYLE_TRIM_OFS)
+#define PAD_CTL_DCYLE_TRIM_RIGHT    (2 << PAD_CTL_DCYLE_TRIM_OFS)
+
+#define PAD_CTL_OBE         (1 << 21)
+#define PAD_CTL_ODE         (1 << 20)
+#define PAD_CTL_IBE         (1 << 19)
+#define PAD_CTL_HYS         (1 << 18)
+#define PAD_CTL_INV         (1 << 17)
+#define PAD_CTL_PKE         (1 << 16)
+
+#define PAD_CTL_SRE_OFS             (14)
+#define PAD_CTL_SRE_LOW_50HZ        (0 << PAD_CTL_SRE_OFS)
+#define PAD_CTL_SRE_LOW_100MHZ      (1 << PAD_CTL_SRE_OFS)
+/* The manual reports the same value for SRE = 01 and SRE = 10 */
+#define PAD_CTL_SRE_HIGH_100MHZ     (2 << PAD_CTL_SRE_OFS)
+#define PAD_CTL_SRE_HIGH_200MHZ     (3 << PAD_CTL_SRE_OFS)
+
+#define PAD_CTL_PUE             (1 << 13)
+
+#define PAD_CTL_PUS_OFS         (11)
+#define PAD_CTL_PUS_100K_DOWN   (0 << PAD_CTL_PUS_OFS)
+#define PAD_CTL_PUS_50K_UP      (1 << PAD_CTL_PUS_OFS)
+#define PAD_CTL_PUS_100K_UP     (2 << PAD_CTL_PUS_OFS)
+#define PAD_CTL_PUS_33K_UP      (3 << PAD_CTL_PUS_OFS)
+#define PAD_CTL_PUS_MASK        (3 << PAD_CTL_PUS_OFS)
+
+#define PAD_CTL_DSE_OFS         (8)
+#define PAD_CTL_DSE_OUT_DISABLE (0 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_240         (1 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_120         (2 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_80          (3 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_60          (4 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_48          (5 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_40          (6 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_34          (7 << PAD_CTL_DSE_OFS)
+#define PAD_CTL_DSE_MASK        (7 << PAD_CTL_DSE_OFS)
+
+#define PAD_CTL_CRPOINT_TRIM    (3 << 6)
+
+#define PAD_CTL_SMC             (1 << 5)
+
+#define PAD_CTL_MUX_MODE_ALT0   (0)
+#define PAD_CTL_MUX_MODE_ALT1   (1)
+#define PAD_CTL_MUX_MODE_ALT2   (2)
+#define PAD_CTL_MUX_MODE_ALT3   (3)
+#define PAD_CTL_MUX_MODE_ALT4   (4)
+#define PAD_CTL_MUX_MODE_ALT5   (5)
+#define PAD_CTL_MUX_MODE_ALT6   (6)
+#define PAD_CTL_MUX_MODE_ALT7   (7)
+#define PAD_CTL_MUX_MODE_MASK   (0xF)
+
+/* UART configuration */
+#define PAD_CTL_UART_TX         (PAD_CTL_OBE | PAD_CTL_PUS_100K_UP |\
+				PAD_CTL_DSE_60 | PAD_CTL_SRE_LOW_100MHZ |\
+				PAD_CTL_MUX_MODE_ALT1)
+#define PAD_CTL_UART_RX_MSCR    (PAD_CTL_PUE | PAD_CTL_IBE |\
+				PAD_CTL_DCYLE_TRIM_RIGHT)
+#define PAD_CTL_UART_RX_IMCR    (PAD_CTL_MUX_MODE_ALT2)
+
+/* CAN0 configuration */
+#define PAD_CTL_CAN_FD0_TX      (PAD_CTL_OBE | PAD_CTL_PUS_50K_UP |\
+				PAD_CTL_PUE | PAD_CTL_DSE_34 |\
+				PAD_CTL_MUX_MODE_ALT1)
+#define PAD_CTL_CAN_FD0_RX_MSCR (PAD_CTL_PUE | PAD_CTL_IBE | PAD_CTL_PUS_50K_UP)
+#define PAD_CTL_CAN_FD0_RX_IMCR (PAD_CTL_MUX_MODE_ALT2)
+
+/* CAN1 configuration */
+#define PAD_CTL_CAN_FD1_TX      (PAD_CTL_OBE | PAD_CTL_PUS_50K_UP |\
+				PAD_CTL_PUE | PAD_CTL_DSE_34 |\
+				PAD_CTL_MUX_MODE_ALT1)
+#define PAD_CTL_CAN_FD1_RX_MSCR (PAD_CTL_PUE | PAD_CTL_IBE | PAD_CTL_PUS_50K_UP)
+#define PAD_CTL_CAN_FD1_RX_IMCR (PAD_CTL_MUX_MODE_ALT3)
+
+/* USDHC configuration  */
+#define PAD_CTL_USDHC_BASE      (PAD_CTL_SRE_HIGH_200MHZ | PAD_CTL_OBE | \
+				PAD_CTL_DSE_34 | PAD_CTL_PKE |  \
+				PAD_CTL_IBE | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE)
+#define PAD_CTL_USDHC_CMD       (PAD_CTL_USDHC_BASE | PAD_CTL_MUX_MODE_ALT1)
+#define PAD_CTL_USDHC_CLK       (PAD_CTL_USDHC_BASE | PAD_CTL_MUX_MODE_ALT2)
+#define PAD_CTL_USDHC_DAT0_3    (PAD_CTL_USDHC_BASE | PAD_CTL_MUX_MODE_ALT2)
+#define PAD_CTL_USDHC_DAT4_7    (PAD_CTL_USDHC_BASE | PAD_CTL_MUX_MODE_ALT3)
+
+/* QSPI configuration */
+#define PAD_CTL_QSPI_BASE         (PAD_CTL_SRE_HIGH_200MHZ | PAD_CTL_OBE | \
+				  PAD_CTL_DSE_34 | PAD_CTL_IBE)
+#define PAD_CTL_QSPI_CLK_BASE     (PAD_CTL_SRE_HIGH_200MHZ | PAD_CTL_DSE_34 | \
+				  PAD_CTL_PUS_100K_UP | PAD_CTL_OBE)
+#define PAD_CTL_QSPI_CK2_MUX      PAD_CTL_MUX_MODE_ALT1
+#define PAD_CTL_QSPI_A_SCK_MUX    PAD_CTL_MUX_MODE_ALT1
+#define PAD_CTL_QSPI_B_SCK_MUX    PAD_CTL_MUX_MODE_ALT1
+#define PAD_CTL_QSPI_A_CS0_MUX    PAD_CTL_MUX_MODE_ALT1
+#define PAD_CTL_QSPI_B_CS0_MUX    PAD_CTL_MUX_MODE_ALT1
+#define PAD_CTL_QSPI_A_CS1_MUX    PAD_CTL_MUX_MODE_ALT1
+#define PAD_CTL_QSPI_B_CS1_MUX    PAD_CTL_MUX_MODE_ALT1
+#define PAD_CTL_QSPI_A_DQS        (PAD_CTL_SRE_HIGH_200MHZ | PAD_CTL_IBE | \
+				  PAD_CTL_PUS_100K_DOWN | PAD_CTL_PUE | \
+				  PAD_CTL_PKE)
+#define PAD_CTL_QSPI_A_DATA0_3    (PAD_CTL_QSPI_BASE | PAD_CTL_MUX_MODE_ALT1)
+#define PAD_CTL_QSPI_A_DATA4_7    (PAD_CTL_QSPI_BASE | PAD_CTL_MUX_MODE_ALT2)
+#define PAD_CTL_QSPI_B_DATA0_3    (PAD_CTL_QSPI_BASE | PAD_CTL_MUX_MODE_ALT1)
+
+/* EIRQ configuration */
+#define PAD_CTL_EIRQ              PAD_CTL_MUX_MODE_ALT2
+
+/* I2C0 - Serial Data Input PA15 */
+#define PAD_CTL_I2C0_MSCR_SDA_PA15    (PAD_CTL_MUX_MODE_ALT1 | PAD_CTL_OBE | \
+				      PAD_CTL_IBE | PAD_CTL_ODE | \
+				      PAD_CTL_DSE_34)
+#define PAD_CTL_I2C0_IMCR_SDA_PA15    (PAD_CTL_MUX_MODE_ALT2)
+
+/* I2C0 - Serial Clock Input PB0 */
+#define PAD_CTL_I2C0_MSCR_SCLK_PB0    (PAD_CTL_MUX_MODE_ALT1 | PAD_CTL_OBE | \
+				      PAD_CTL_IBE | PAD_CTL_ODE | \
+				      PAD_CTL_DSE_34)
+#define PAD_CTL_I2C0_IMCR_SCLK_PB0    (PAD_CTL_MUX_MODE_ALT2)
+
+/* I2C0 - Serial Data Input PG3 */
+#define PAD_CTL_I2C0_MSCR_SDA_PG3     (PAD_CTL_MUX_MODE_ALT2 | PAD_CTL_OBE | \
+				      PAD_CTL_IBE | PAD_CTL_ODE | \
+				      PAD_CTL_DSE_34)
+#define PAD_CTL_I2C0_IMCR_SDA_PG3     (PAD_CTL_MUX_MODE_ALT3)
+
+/* I2C0 - Serial Clock Input PG4 */
+#define PAD_CTL_I2C0_MSCR_SCLK_PG4    (PAD_CTL_MUX_MODE_ALT2 | PAD_CTL_OBE | \
+				      PAD_CTL_IBE | PAD_CTL_ODE | \
+				      PAD_CTL_DSE_34)
+#define PAD_CTL_I2C0_IMCR_SCLK_PG4    (PAD_CTL_MUX_MODE_ALT3)
+
+/* I2C1 - Serial Data Input */
+#define  PAD_CTL_I2C1_MSCR_SDA  (PAD_CTL_MUX_MODE_ALT2 | PAD_CTL_OBE | \
+				PAD_CTL_IBE | PAD_CTL_ODE | PAD_CTL_DSE_34)
+#define PAD_CTL_I2C1_IMCR_SDA   (PAD_CTL_MUX_MODE_ALT3)
+
+/* I2C1 - Serial Clock Input */
+#define  PAD_CTL_I2C1_MSCR_SCLK (PAD_CTL_MUX_MODE_ALT2 | PAD_CTL_OBE | \
+				PAD_CTL_IBE | PAD_CTL_ODE | PAD_CTL_DSE_34)
+#define PAD_CTL_I2C1_IMCR_SCLK  (PAD_CTL_MUX_MODE_ALT3)
+
+/* I2C2 - Serial Data Input */
+#define  PAD_CTL_I2C2_MSCR_SDA  (PAD_CTL_MUX_MODE_ALT1 | PAD_CTL_OBE | \
+				PAD_CTL_IBE | PAD_CTL_ODE | PAD_CTL_DSE_34)
+#define PAD_CTL_I2C2_IMCR_SDA   (PAD_CTL_MUX_MODE_ALT2)
+
+/* I2C2 - Serial Clock Input */
+#define  PAD_CTL_I2C2_MSCR_SCLK (PAD_CTL_MUX_MODE_ALT1 | PAD_CTL_OBE | \
+				PAD_CTL_IBE | PAD_CTL_ODE | PAD_CTL_DSE_34)
+#define PAD_CTL_I2C2_IMCR_SCLK  (PAD_CTL_MUX_MODE_ALT2)
+
+/* ENET CFG1 = 0x203701 */
+#define PAD_CTL_ENET_CFG1       (PAD_CTL_DSE_34 | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+                                PAD_CTL_OBE | PAD_CTL_MUX_MODE_ALT1)
+
+/* ENET CFG2 = 0x20c701 */
+#define PAD_CTL_ENET_CFG2       (PAD_CTL_DSE_34 | PAD_CTL_SRE_HIGH_200MHZ | \
+                                PAD_CTL_OBE | PAD_CTL_MUX_MODE_ALT1)
+
+/* ENET CFG3 = 0x28c701 */
+#define PAD_CTL_ENET_CFG3       (PAD_CTL_DSE_34 | PAD_CTL_SRE_HIGH_200MHZ | \
+                                PAD_CTL_OBE | PAD_CTL_IBE | PAD_CTL_MUX_MODE_ALT1)
+
+/* ENET CFG7 = 0x8c700 */
+#define PAD_CTL_ENET_CFG4       (PAD_CTL_DSE_34 | PAD_CTL_SRE_HIGH_200MHZ | PAD_CTL_IBE)
+
+/* DCU CFG = 0x20C101 */
+#define PAD_CTL_DCU_CFG         (PAD_CTL_DSE_80 | PAD_CTL_SRE_HIGH_200MHZ | \
+				PAD_CTL_OBE | PAD_CTL_IBE | \
+				PAD_CTL_MUX_MODE_ALT1)
+
+#define PAD_CTL_DCU_CLK_CFG_DSE_DISABLE (PAD_CTL_SRE_HIGH_200MHZ | \
+					PAD_CTL_OBE | PAD_CTL_IBE | \
+					PAD_CTL_MUX_MODE_ALT1)
+
+/* VIU IMCR = 0x00000002 */
+#define PAD_CTL_VIU_CFG         (PAD_CTL_MUX_MODE_ALT2)
+
+/* VIU MSCR = 0x00000002 */
+#define PAD_CTL_VIU_IBE         (PAD_CTL_IBE)
+
+/* SPI 0-3 */
+#define PAD_CTL_SPI_MSCR_CSx    (PAD_CTL_OBE | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_DSE_34 | PAD_CTL_PUE)
+
+#define PAD_CTL_SPI_MSCR_SCK    (PAD_CTL_OBE | PAD_CTL_DSE_34 | \
+				PAD_CTL_MUX_MODE_ALT1)
+
+#define PAD_CTL_SPI_MSCR_SOUT   (PAD_CTL_OBE | PAD_CTL_DSE_34 | \
+				PAD_CTL_MUX_MODE_ALT1)
+
+#define PAD_CTL_SPI_MSCR_SIN    (PAD_CTL_PUE | PAD_CTL_IBE | \
+				PAD_CTL_PUS_50K_UP)
+
+#define PAD_CTL_SPI_IMCR_SIN    (PAD_CTL_MUX_MODE_ALT2)
+
+/* MSCR register numbers associated to port or function */
+#define S32V234_MSCR_PA0        0
+#define S32V234_MSCR_PA1        1
+#define S32V234_MSCR_PA2        2
+#define S32V234_MSCR_PA3        3
+#define S32V234_MSCR_PA4        4
+#define S32V234_MSCR_PA5        5
+#define S32V234_MSCR_PA6        6
+#define S32V234_MSCR_PA7        7
+#define S32V234_MSCR_PA8        8
+#define S32V234_MSCR_PA9        9
+#define S32V234_MSCR_PA10       10
+#define S32V234_MSCR_PA11       11
+#define S32V234_MSCR_PA12       12
+#define S32V234_MSCR_PA13       13
+#define S32V234_MSCR_PA14       14
+#define S32V234_MSCR_PA15       15
+#define S32V234_MSCR_PB0        16
+#define S32V234_MSCR_PB1        17
+#define S32V234_MSCR_PB2        18
+#define S32V234_MSCR_PB3        19
+#define S32V234_MSCR_PB4        20
+#define S32V234_MSCR_PB5        21
+#define S32V234_MSCR_PB6        22
+#define S32V234_MSCR_PB7        23
+#define S32V234_MSCR_PB8        24
+#define S32V234_MSCR_PB9        25
+#define S32V234_MSCR_PB10       26
+#define S32V234_MSCR_PB11       27
+#define S32V234_MSCR_PB12       28
+#define S32V234_MSCR_PB13       29
+#define S32V234_MSCR_PB14       30
+#define S32V234_MSCR_PB15       31
+#define S32V234_MSCR_PC0        32
+#define S32V234_MSCR_PC1        33
+#define S32V234_MSCR_PC2        34
+#define S32V234_MSCR_PC3        35
+#define S32V234_MSCR_PC4        36
+#define S32V234_MSCR_PC5        37
+#define S32V234_MSCR_PC6        38
+#define S32V234_MSCR_PC7        39
+#define S32V234_MSCR_PC8        40
+#define S32V234_MSCR_PC9        41
+#define S32V234_MSCR_PC10       42
+#define S32V234_MSCR_PC11       43
+#define S32V234_MSCR_PC12       44
+#define S32V234_MSCR_PC13       45
+#define S32V234_MSCR_PC14       46
+#define S32V234_MSCR_PC15       47
+#define S32V234_MSCR_PD0        48
+#define S32V234_MSCR_PD1        49
+#define S32V234_MSCR_PD2        50
+#define S32V234_MSCR_PD3        51
+#define S32V234_MSCR_PD4        52
+#define S32V234_MSCR_PD5        53
+#define S32V234_MSCR_PD6        54
+#define S32V234_MSCR_PD7        55
+#define S32V234_MSCR_PD8        56
+#define S32V234_MSCR_PD9        57
+#define S32V234_MSCR_PD10       58
+#define S32V234_MSCR_PD11       59
+#define S32V234_MSCR_PD12       60
+#define S32V234_MSCR_PD13       61
+#define S32V234_MSCR_PD14       62
+#define S32V234_MSCR_PD15       63
+#define S32V234_MSCR_PE0        64
+#define S32V234_MSCR_PE1        65
+#define S32V234_MSCR_PE2        66
+#define S32V234_MSCR_PE3        67
+#define S32V234_MSCR_PE4        68
+#define S32V234_MSCR_PE5        69
+#define S32V234_MSCR_PE6        70
+#define S32V234_MSCR_PE7        71
+#define S32V234_MSCR_PE8        72
+#define S32V234_MSCR_PE9        73
+#define S32V234_MSCR_PE10       74
+#define S32V234_MSCR_PE11       75
+#define S32V234_MSCR_PE12       76
+#define S32V234_MSCR_PE13       77
+#define S32V234_MSCR_PE14       78
+#define S32V234_MSCR_PE15       79
+#define S32V234_MSCR_PF0        80
+#define S32V234_MSCR_PF1        81
+#define S32V234_MSCR_PF2        82
+#define S32V234_MSCR_PF3        83
+#define S32V234_MSCR_PF4        84
+#define S32V234_MSCR_PF5        85
+#define S32V234_MSCR_PF6        86
+#define S32V234_MSCR_PF7        87
+#define S32V234_MSCR_PF8        88
+#define S32V234_MSCR_PF9        89
+#define S32V234_MSCR_PF10       90
+#define S32V234_MSCR_PF11       91
+#define S32V234_MSCR_PF12       92
+#define S32V234_MSCR_PF13       93
+#define S32V234_MSCR_PF14       94
+#define S32V234_MSCR_PF15       95
+#define S32V234_MSCR_PG0        96
+#define S32V234_MSCR_PG1        97
+#define S32V234_MSCR_PG2        98
+#define S32V234_MSCR_PG3        99
+#define S32V234_MSCR_PG4        100
+#define S32V234_MSCR_PG5        101
+#define S32V234_MSCR_PG6        102
+#define S32V234_MSCR_PG7        103
+#define S32V234_MSCR_PG8        104
+#define S32V234_MSCR_PG9        105
+#define S32V234_MSCR_PG10       106
+#define S32V234_MSCR_PG11       107
+#define S32V234_MSCR_PG12       108
+#define S32V234_MSCR_PG13       109
+#define S32V234_MSCR_PG14       110
+#define S32V234_MSCR_PG15       111
+#define S32V234_MSCR_PH0        112
+#define S32V234_MSCR_PH1        113
+#define S32V234_MSCR_PH2        114
+#define S32V234_MSCR_PH3        115
+#define S32V234_MSCR_PH4        116
+#define S32V234_MSCR_PH5        117
+#define S32V234_MSCR_PH6        118
+#define S32V234_MSCR_PH7        119
+#define S32V234_MSCR_PH8        120
+#define S32V234_MSCR_PH9        121
+#define S32V234_MSCR_PH10       122
+#define S32V234_MSCR_PH11       123
+#define S32V234_MSCR_PH12       124
+#define S32V234_MSCR_PH13       125
+#define S32V234_MSCR_PH14       126
+#define S32V234_MSCR_PH15       127
+#define S32V234_MSCR_PJ0        128
+#define S32V234_MSCR_PJ1        129
+#define S32V234_MSCR_PJ2        130
+#define S32V234_MSCR_PJ3        131
+#define S32V234_MSCR_PJ4        132
+#define S32V234_MSCR_PJ5        133
+#define S32V234_MSCR_PJ6        134
+#define S32V234_MSCR_PJ7        135
+#define S32V234_MSCR_PJ8        136
+#define S32V234_MSCR_PJ9        137
+#define S32V234_MSCR_PJ10       138
+#define S32V234_MSCR_PJ11       139
+#define S32V234_MSCR_PJ12       140
+#define S32V234_MSCR_PJ13       141
+#define S32V234_MSCR_PJ14       142
+#define S32V234_MSCR_PJ15       143
+#define S32V234_MSCR_PK0        144
+#define S32V234_MSCR_PK1        145
+#define S32V234_MSCR_PK2        146
+#define S32V234_MSCR_PK3        147
+#define S32V234_MSCR_PK4        148
+#define S32V234_MSCR_PK5        149
+#define S32V234_MSCR_PK6        150
+#define S32V234_MSCR_PK7        151
+#define S32V234_MSCR_PK8        152
+#define S32V234_MSCR_PK9        153
+#define S32V234_MSCR_PK10       154
+#define S32V234_MSCR_PK11       155
+#define S32V234_MSCR_PK12       156
+#define S32V234_MSCR_PK13       157
+#define S32V234_MSCR_PK14       158
+#define S32V234_MSCR_PK15       159
+#define S32V234_MSCR_PL0        160
+#define S32V234_MSCR_PL1        161
+#define S32V234_MSCR_PL2        162
+#define S32V234_MSCR_PL3        163
+#define S32V234_MSCR_PL4        164
+#define S32V234_MSCR_PL5        165
+#define S32V234_MSCR_PL8        166
+
+#define S32V234_IMCR_FlexTimer0_CH0    512
+#define S32V234_IMCR_FlexTimer0_CH1    513
+#define S32V234_IMCR_FlexTimer0_CH2    514
+#define S32V234_IMCR_FlexTimer0_CH3    515
+#define S32V234_IMCR_FlexTimer0_CH4    516
+#define S32V234_IMCR_FlexTimer0_CH5    517
+#define S32V234_IMCR_FlexTimer0_EXTCLK 520
+#define S32V234_IMCR_FlexTimer1_CH0    521
+#define S32V234_IMCR_FlexTimer1_CH1    522
+#define S32V234_IMCR_FlexTimer1_CH2    523
+#define S32V234_IMCR_FlexTimer1_CH3    524
+#define S32V234_IMCR_FlexTimer1_CH4    525
+#define S32V234_IMCR_FlexTimer1_CH5    526
+#define S32V234_IMCR_FlexTimer1_EXTCLK 529
+#define S32V234_IMCR_LFAST_REF_CLK     550
+#define S32V234_IMCR_BOOT_BOOTMOD0     570
+#define S32V234_IMCR_BOOT_BOOTMOD1     571
+#define S32V234_IMCR_SIUL_EIRQ0        590
+#define S32V234_IMCR_SIUL_EIRQ1        591
+#define S32V234_IMCR_SIUL_EIRQ2        592
+#define S32V234_IMCR_SIUL_EIRQ3        593
+#define S32V234_IMCR_SIUL_EIRQ4        594
+#define S32V234_IMCR_SIUL_EIRQ5        595
+#define S32V234_IMCR_SIUL_EIRQ6        596
+#define S32V234_IMCR_SIUL_EIRQ7        597
+#define S32V234_IMCR_SIUL_EIRQ8        598
+#define S32V234_IMCR_SIUL_EIRQ9        599
+#define S32V234_IMCR_SIUL_EIRQ10       600
+#define S32V234_IMCR_SIUL_EIRQ11       601
+#define S32V234_IMCR_SIUL_EIRQ12       602
+#define S32V234_IMCR_SIUL_EIRQ13       603
+#define S32V234_IMCR_SIUL_EIRQ14       604
+#define S32V234_IMCR_SIUL_EIRQ15       605
+#define S32V234_IMCR_SIUL_EIRQ16       606
+#define S32V234_IMCR_SIUL_EIRQ17       607
+#define S32V234_IMCR_SIUL_EIRQ18       608
+#define S32V234_IMCR_SIUL_EIRQ19       609
+#define S32V234_IMCR_SIUL_EIRQ20       610
+#define S32V234_IMCR_SIUL_EIRQ21       611
+#define S32V234_IMCR_SIUL_EIRQ22       612
+#define S32V234_IMCR_SIUL_EIRQ23       613
+#define S32V234_IMCR_SIUL_EIRQ24       614
+#define S32V234_IMCR_SIUL_EIRQ25       615
+#define S32V234_IMCR_SIUL_EIRQ26       616
+#define S32V234_IMCR_SIUL_EIRQ27       617
+#define S32V234_IMCR_SIUL_EIRQ28       618
+#define S32V234_IMCR_SIUL_EIRQ29       619
+#define S32V234_IMCR_SIUL_EIRQ30       620
+#define S32V234_IMCR_SIUL_EIRQ31       621
+#define S32V234_IMCR_VIU0_HSYNC        622
+#define S32V234_IMCR_VIU0_VSYNC        623
+#define S32V234_IMCR_VIU0_PCLK         624
+#define S32V234_IMCR_VIU0_D4           629
+#define S32V234_IMCR_VIU0_D5           630
+#define S32V234_IMCR_VIU0_D6           631
+#define S32V234_IMCR_VIU0_D7           632
+#define S32V234_IMCR_VIU0_D8           633
+#define S32V234_IMCR_VIU0_D9           634
+#define S32V234_IMCR_VIU0_D10          635
+#define S32V234_IMCR_VIU0_D11          636
+#define S32V234_IMCR_VIU0_D12          637
+#define S32V234_IMCR_VIU0_D13          638
+#define S32V234_IMCR_VIU0_D14          639
+#define S32V234_IMCR_VIU0_D15          640
+#define S32V234_IMCR_VIU0_D16          641
+#define S32V234_IMCR_VIU0_D17          642
+#define S32V234_IMCR_VIU0_D18          643
+#define S32V234_IMCR_VIU0_D19          644
+#define S32V234_IMCR_VIU0_D20          645
+#define S32V234_IMCR_VIU0_D21          646
+#define S32V234_IMCR_VIU0_D22          647
+#define S32V234_IMCR_VIU0_D23          648
+#define S32V234_IMCR_VIU1_HSYNC        657
+#define S32V234_IMCR_VIU1_VSYNC        658
+#define S32V234_IMCR_VIU1_PCLK         659
+#define S32V234_IMCR_VIU1_D8           668
+#define S32V234_IMCR_VIU1_D9           669
+#define S32V234_IMCR_VIU1_D10          670
+#define S32V234_IMCR_VIU1_D11          671
+#define S32V234_IMCR_VIU1_D12          672
+#define S32V234_IMCR_VIU1_D13          673
+#define S32V234_IMCR_VIU1_D14          674
+#define S32V234_IMCR_VIU1_D15          675
+#define S32V234_IMCR_VIU1_D16          676
+#define S32V234_IMCR_VIU1_D17          677
+#define S32V234_IMCR_VIU1_D18          678
+#define S32V234_IMCR_VIU1_D19          679
+#define S32V234_IMCR_VIU1_D20          680
+#define S32V234_IMCR_VIU1_D21          681
+#define S32V234_IMCR_VIU1_D22          682
+#define S32V234_IMCR_VIU1_D23          683
+#define S32V234_IMCR_CAN_FD0_RXD       700
+#define S32V234_IMCR_CAN_FD1_RXD       701
+#define S32V234_IMCR_UART0_RXD         712
+#define S32V234_IMCR_UART1_RXD         714
+#define S32V234_IMCR_IIC0_CLK          780
+#define S32V234_IMCR_IIC0_DATA         781
+#define S32V234_IMCR_IIC1_CLK          782
+#define S32V234_IMCR_IIC1_DATA         783
+#define S32V234_IMCR_IIC2_CLK          784
+#define S32V234_IMCR_IIC2_DATA         785
+#define S32V234_IMCR_SPI0_SIN          800
+#define S32V234_IMCR_SPI0_SCK          801
+#define S32V234_IMCR_SPI0_CS0          802
+#define S32V234_IMCR_SPI1_SIN          803
+#define S32V234_IMCR_SPI1_SCK          804
+#define S32V234_IMCR_SPI1_CS0          805
+#define S32V234_IMCR_SPI2_SIN          806
+#define S32V234_IMCR_SPI2_SCK          807
+#define S32V234_IMCR_SPI2_CS0          808
+#define S32V234_IMCR_SPI3_SIN          809
+#define S32V234_IMCR_SPI3_SCK          810
+#define S32V234_IMCR_SPI3_CS0          811
+#define S32V234_IMCR_QSPI_A_DQS        819
+#define S32V234_IMCR_QSPI_A_DATA0      820
+#define S32V234_IMCR_QSPI_A_DATA1      821
+#define S32V234_IMCR_QSPI_A_DATA2      822
+#define S32V234_IMCR_QSPI_A_DATA3      823
+#define S32V234_IMCR_QSPI_A_DATA4      824
+#define S32V234_IMCR_QSPI_A_DATA5      825
+#define S32V234_IMCR_QSPI_A_DATA6      826
+#define S32V234_IMCR_QSPI_A_DATA7      827
+#define S32V234_IMCR_QSPI_B_DQS        828
+#define S32V234_IMCR_QSPI_B_DATA0      829
+#define S32V234_IMCR_QSPI_B_DATA1      830
+#define S32V234_IMCR_QSPI_B_DATA2      831
+#define S32V234_IMCR_QSPI_B_DATA3      832
+#define S32V234_IMCR_USDHC_WP          900
+#define S32V234_IMCR_USDHC_CMD         901
+#define S32V234_IMCR_USDHC_CLK         902
+#define S32V234_IMCR_USDHC_DAT0        903
+#define S32V234_IMCR_USDHC_DAT1        904
+#define S32V234_IMCR_USDHC_DAT2        905
+#define S32V234_IMCR_USDHC_DAT3        906
+#define S32V234_IMCR_USDHC_DAT4        907
+#define S32V234_IMCR_USDHC_DAT5        908
+#define S32V234_IMCR_USDHC_DAT6        909
+#define S32V234_IMCR_USDHC_DAT7        910
+#define S32V234_IMCR_Ethernet_RX_ER    970
+#define S32V234_IMCR_Ethernet_COL      971
+#define S32V234_IMCR_Ethernet_CRS      972
+#define S32V234_IMCR_Ethernet_RX_DV    973
+#define S32V234_IMCR_Ethernet_RX_D0    974
+#define S32V234_IMCR_Ethernet_RX_D1    975
+#define S32V234_IMCR_Ethernet_RX_D2    976
+#define S32V234_IMCR_Ethernet_RX_D3    977
+#define S32V234_IMCR_Ethernet_TX_CLK   978
+#define S32V234_IMCR_Ethernet_RX_CLK   979
+#define S32V234_IMCR_Ethernet_MDIO     981
+#define S32V234_IMCR_Ethernet_TIMER0   982
+#define S32V234_IMCR_Ethernet_TIMER1   983
+#define S32V234_IMCR_Ethernet_TIMER2   984
+#define S32V234_IMCR_FlexRay_CA_RX     1012
+#define S32V234_IMCR_FlexRay_CB_RX     1013
+#define S32V234_IMCR_SSE_IN0           1018
+#define S32V234_IMCR_SSE_IN1           1019
+#define S32V234_IMCR_SSE_IN2           1020
+#define S32V234_IMCR_SSE_IN3           1021
+
+/* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the IMCR_IDX
+ * instead of MSCR_IDX, add 512 to it as the Reference Manual states.
+ */
+
+/* UART configuration */
+#define S32V234_PAD_PA12__UART0_TXD     S32V234_MSCR_PA12 PAD_CTL_UART_TX
+#define S32V234_PAD_PA11__UART0_RXD_OUT S32V234_MSCR_PA11 PAD_CTL_UART_RX_MSCR
+#define S32V234_PAD_PA11__UART0_RXD_IN  S32V234_IMCR_UART0_RXD \
+					PAD_CTL_UART_RX_IMCR
+
+#define S32V234_PAD_PA14__UART1_TXD     S32V234_MSCR_PA14 PAD_CTL_UART_TX
+#define S32V234_PAD_PA13__UART1_RXD_OUT S32V234_MSCR_PA13 PAD_CTL_UART_RX_MSCR
+#define S32V234_PAD_PA13__UART1_RXD_IN  S32V234_IMCR_UART1_RXD \
+					PAD_CTL_UART_RX_IMCR
+
+/* CAN0 configuration */
+#define S32V234_PAD_PA2__CAN_FD0_TXD     S32V234_MSCR_PA2 PAD_CTL_CAN_FD0_TX
+#define S32V234_PAD_PA3__CAN_FD0_RXD_OUT S32V234_MSCR_PA3 \
+					 PAD_CTL_CAN_FD0_RX_MSCR
+#define S32V234_PAD_PA3__CAN_FD0_RXD_IN  S32V234_IMCR_CAN_FD0_RXD \
+					 PAD_CTL_CAN_FD0_RX_IMCR
+
+/* CAN1 configuration */
+#define S32V234_PAD_PA4__CAN_FD1_TXD     S32V234_MSCR_PA4 PAD_CTL_CAN_FD1_TX
+#define S32V234_PAD_PA5__CAN_FD1_RXD_OUT S32V234_MSCR_PA5 \
+					 PAD_CTL_CAN_FD1_RX_MSCR
+#define S32V234_PAD_PA5__CAN_FD1_RXD_IN  S32V234_IMCR_CAN_FD1_RXD \
+					 PAD_CTL_CAN_FD1_RX_IMCR
+
+/* uSDHC configuration */
+#define S32V234_PAD_PK6__USDHC_CLK_OUT   S32V234_MSCR_PK6 PAD_CTL_USDHC_CLK
+#define S32V234_PAD_PK6__USDHC_CLK_IN    S32V234_IMCR_USDHC_CLK \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PK7__USDHC_CMD_OUT   S32V234_MSCR_PK7 PAD_CTL_USDHC_CMD
+#define S32V234_PAD_PK7__USDHC_CMD_IN    S32V234_IMCR_USDHC_CMD \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PK8__USDHC_DAT0_OUT  S32V234_MSCR_PK8 PAD_CTL_USDHC_DAT0_3
+#define S32V234_PAD_PK8__USDHC_DAT0_IN   S32V234_IMCR_USDHC_DAT0 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PK9__USDHC_DAT1_OUT  S32V234_MSCR_PK9 PAD_CTL_USDHC_DAT0_3
+#define S32V234_PAD_PK9__USDHC_DAT1_IN   S32V234_IMCR_USDHC_DAT1 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PK10__USDHC_DAT2_OUT S32V234_MSCR_PK10 PAD_CTL_USDHC_DAT0_3
+#define S32V234_PAD_PK10__USDHC_DAT2_IN  S32V234_IMCR_USDHC_DAT2 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PK11__USDHC_DAT3_OUT S32V234_MSCR_PK11 PAD_CTL_USDHC_DAT0_3
+#define S32V234_PAD_PK11__USDHC_DAT3_IN  S32V234_IMCR_USDHC_DAT3 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PK15__USDHC_DAT4_OUT S32V234_MSCR_PK15 PAD_CTL_USDHC_DAT4_7
+#define S32V234_PAD_PK15__USDHC_DAT4_IN  S32V234_IMCR_USDHC_DAT4 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PL0__USDHC_DAT5_OUT  S32V234_MSCR_PL0 PAD_CTL_USDHC_DAT4_7
+#define S32V234_PAD_PL0__USDHC_DAT5_IN   S32V234_IMCR_USDHC_DAT5 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PL1__USDHC_DAT6_OUT  S32V234_MSCR_PL1 PAD_CTL_USDHC_DAT4_7
+#define S32V234_PAD_PL1__USDHC_DAT6_IN   S32V234_IMCR_USDHC_DAT6 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+#define S32V234_PAD_PL2__USDHC_DAT7_OUT  S32V234_MSCR_PL2 PAD_CTL_USDHC_DAT4_7
+#define S32V234_PAD_PL2__USDHC_DAT7_IN   S32V234_IMCR_USDHC_DAT7 \
+					 PAD_CTL_MUX_MODE_ALT3
+
+/* QSPI configuration */
+#define S32V234_PAD_PK7__QSPI_A_DQS        S32V234_IMCR_QSPI_A_DQS \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PK14__QSPI_B_DQS       S32V234_IMCR_QSPI_B_DQS \
+					   PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PK8__QSPI_A_DATA0_IN   S32V234_IMCR_QSPI_A_DATA0 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PK8__QSPI_A_DATA0_OUT  S32V234_MSCR_PK8 \
+					   PAD_CTL_QSPI_A_DATA0_3
+
+#define S32V234_PAD_PK9__QSPI_A_DATA1_IN   S32V234_IMCR_QSPI_A_DATA1 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PK9__QSPI_A_DATA1_OUT  S32V234_MSCR_PK9 \
+					   PAD_CTL_QSPI_A_DATA0_3
+
+#define S32V234_PAD_PK10__QSPI_A_DATA2_IN  S32V234_IMCR_QSPI_A_DATA2 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PK10__QSPI_A_DATA2_OUT S32V234_MSCR_PK10 \
+					   PAD_CTL_QSPI_A_DATA0_3
+
+#define S32V234_PAD_PK11__QSPI_A_DATA3_IN  S32V234_IMCR_QSPI_A_DATA3 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PK11__QSPI_A_DATA3_OUT S32V234_MSCR_PK11 \
+					   PAD_CTL_QSPI_A_DATA0_3
+
+#define S32V234_PAD_PK15__QSPI_A_DATA4_IN  S32V234_IMCR_QSPI_A_DATA4 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PK15__QSPI_A_DATA4_OUT S32V234_MSCR_PK15 \
+					   PAD_CTL_QSPI_A_DATA4_7
+
+#define S32V234_PAD_PL0__QSPI_A_DATA5_IN   S32V234_IMCR_QSPI_A_DATA5 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PL0__QSPI_A_DATA5_OUT  S32V234_MSCR_PL0 \
+					   PAD_CTL_QSPI_A_DATA4_7
+
+#define S32V234_PAD_PL1__QSPI_A_DATA6_IN   S32V234_IMCR_QSPI_A_DATA6 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PL1__QSPI_A_DATA6_OUT  S32V234_MSCR_PL1 \
+					   PAD_CTL_QSPI_A_DATA4_7
+
+#define S32V234_PAD_PL2__QSPI_A_DATA7_IN   S32V234_IMCR_QSPI_A_DATA7 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PL2__QSPI_A_DATA7_OUT  S32V234_MSCR_PL2 \
+					   PAD_CTL_QSPI_A_DATA4_7
+
+#define S32V234_PAD_PK15__QSPI_B_DATA0_IN  S32V234_IMCR_QSPI_B_DATA0 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PK15__QSPI_B_DATA0_OUT S32V234_MSCR_PK15 \
+					   PAD_CTL_QSPI_B_DATA0_3
+
+#define S32V234_PAD_PL0__QSPI_B_DATA1_IN   S32V234_IMCR_QSPI_B_DATA1 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PL0__QSPI_B_DATA1_OUT  S32V234_MSCR_PL0 \
+					   PAD_CTL_QSPI_B_DATA0_3
+
+#define S32V234_PAD_PL1__QSPI_B_DATA2_IN   S32V234_IMCR_QSPI_B_DATA2 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PL1__QSPI_B_DATA2_OUT  S32V234_MSCR_PL1 \
+					   PAD_CTL_QSPI_B_DATA0_3
+
+#define S32V234_PAD_PL2__QSPI_B_DATA3_IN   S32V234_IMCR_QSPI_B_DATA3 \
+					   PAD_CTL_MUX_MODE_ALT2
+#define S32V234_PAD_PL2__QSPI_B_DATA3_OUT  S32V234_MSCR_PL2 \
+					   PAD_CTL_QSPI_B_DATA0_3
+
+#define S32V234_PAD_PF12__QSPI_A_CS1       S32V234_MSCR_PF12 \
+					   (PAD_CTL_QSPI_CLK_BASE | \
+					   PAD_CTL_QSPI_A_CS1_MUX)
+#define S32V234_PAD_PF13__QSPI_B_CS1       S32V234_MSCR_PF13 \
+					   (PAD_CTL_QSPI_CLK_BASE | \
+					   PAD_CTL_QSPI_B_CS1_MUX)
+
+#define S32V234_PAD_PK5__QSPI_A_CS0        S32V234_MSCR_PK5 \
+					   (PAD_CTL_QSPI_CLK_BASE | \
+					   PAD_CTL_QSPI_A_CS0_MUX)
+#define S32V234_PAD_PK6__QSPI_A_SCK        S32V234_MSCR_PK6 \
+					   (PAD_CTL_QSPI_CLK_BASE | \
+					   PAD_CTL_QSPI_A_SCK_MUX)
+
+#define S32V234_PAD_PK12__QSPI_B_CS0       S32V234_MSCR_PK12 \
+					   (PAD_CTL_QSPI_CLK_BASE | \
+					   PAD_CTL_QSPI_B_CS0_MUX)
+#define S32V234_PAD_PK13__QSPI_B_SCK       S32V234_MSCR_PK13 \
+					   (PAD_CTL_QSPI_CLK_BASE | \
+					   PAD_CTL_QSPI_B_SCK_MUX)
+
+#define S32V234_PAD_PK13__QSPI_CK2         S32V234_MSCR_PK13 \
+					   (PAD_CTL_QSPI_CLK_BASE | \
+					   PAD_CTL_QSPI_CK2_MUX)
+
+/* I2C configuration */
+#define S32V234_PAD_PA15__I2C0_DATA_OUT S32V234_MSCR_PA15 \
+					PAD_CTL_I2C0_MSCR_SDA_PA15
+#define S32V234_PAD_PA15__I2C0_DATA_IN  S32V234_IMCR_IIC0_DATA \
+					PAD_CTL_I2C0_IMCR_SDA_PA15
+
+#define S32V234_PAD_PB0__I2C0_SCLK_OUT  S32V234_MSCR_PB0 \
+					PAD_CTL_I2C0_MSCR_SCLK_PB0
+#define S32V234_PAD_PB0__I2C0_SCLK_IN   S32V234_IMCR_IIC0_CLK \
+					PAD_CTL_I2C0_IMCR_SCLK_PB0
+
+#define S32V234_PAD_PG3__I2C0_DATA_OUT  S32V234_MSCR_PG3 \
+					PAD_CTL_I2C0_MSCR_SDA_PG3
+#define S32V234_PAD_PG3__I2C0_DATA_IN   S32V234_IMCR_IIC0_DATA \
+					PAD_CTL_I2C0_IMCR_SDA_PG3
+
+#define S32V234_PAD_PG4__I2C0_SCLK_OUT  S32V234_MSCR_PG4 \
+					PAD_CTL_I2C0_MSCR_SCLK_PG4
+#define S32V234_PAD_PG4__I2C0_SCLK_IN   S32V234_IMCR_IIC0_CLK \
+					PAD_CTL_I2C0_IMCR_SCLK_PG4
+
+#define S32V234_PAD_PG5__I2C1_DATA_OUT  S32V234_MSCR_PG5 \
+					PAD_CTL_I2C1_MSCR_SDA
+#define S32V234_PAD_PG5__I2C1_DATA_IN   S32V234_IMCR_IIC1_DATA \
+					PAD_CTL_I2C1_IMCR_SDA
+
+#define S32V234_PAD_PG6__I2C1_SCLK_OUT  S32V234_MSCR_PG6 \
+					PAD_CTL_I2C1_MSCR_SCLK
+#define S32V234_PAD_PG6__I2C1_SCLK_IN   S32V234_IMCR_IIC1_CLK \
+					PAD_CTL_I2C1_IMCR_SCLK
+
+#define S32V234_PAD_PB3__I2C2_DATA_OUT  S32V234_MSCR_PB3 \
+					PAD_CTL_I2C2_MSCR_SDA
+#define S32V234_PAD_PB3__I2C2_DATA_IN   S32V234_IMCR_IIC2_DATA \
+					PAD_CTL_I2C2_IMCR_SDA
+
+#define S32V234_PAD_PB4__I2C2_SCLK_OUT  S32V234_MSCR_PB4 \
+					PAD_CTL_I2C2_MSCR_SCLK
+#define S32V234_PAD_PB4__I2C2_SCLK_IN   S32V234_IMCR_IIC2_CLK \
+					PAD_CTL_I2C2_IMCR_SCLK
+
+/* ENET configuration */
+#define S32V234_PAD_PC13__MDC       S32V234_MSCR_PC13 PAD_CTL_ENET_CFG2
+
+#define S32V234_PAD_PC14__MDIO_OUT  S32V234_MSCR_PC14 PAD_CTL_ENET_CFG3
+#define S32v234_PAD_PC14__MDIO_IN   S32V234_IMCR_Ethernet_MDIO \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PC15__TXCLK_OUT S32V234_MSCR_PC15 PAD_CTL_ENET_CFG1
+#define S32V234_PAD_PC15__TXCLK_IN  S32V234_IMCR_Ethernet_TX_CLK \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PD0__RXCLK_OUT  S32V234_MSCR_PD0 PAD_CTL_ENET_CFG4
+#define S32V234_PAD_PD0__RXCLK_IN   S32V234_IMCR_Ethernet_RX_CLK \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PD1__RX_D0_OUT  S32V234_MSCR_PD1 PAD_CTL_ENET_CFG4
+#define S32V234_PAD_PD1__RX_D0_IN   S32V234_IMCR_Ethernet_RX_D0 \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PD2__RX_D1_OUT  S32V234_MSCR_PD2 PAD_CTL_ENET_CFG4
+#define S32V234_PAD_PD2__RX_D1_IN   S32V234_IMCR_Ethernet_RX_D1 \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PD3__RX_D2_OUT  S32V234_MSCR_PD3 PAD_CTL_ENET_CFG4
+#define S32V234_PAD_PD3__RX_D2_IN   S32V234_IMCR_Ethernet_RX_D2 \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PD4__RX_D3_OUT  S32V234_MSCR_PD4 PAD_CTL_ENET_CFG4
+#define S32V234_PAD_PD4__RX_D3_IN   S32V234_IMCR_Ethernet_RX_D3 \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PD4__RX_DV_OUT  S32V234_MSCR_PD5 PAD_CTL_ENET_CFG4
+#define S32V234_PAD_PD4__RX_DV_IN   S32V234_IMCR_Ethernet_RX_DV \
+				    PAD_CTL_MUX_MODE_ALT2
+
+#define S32V234_PAD_PD7__TX_D0_OUT  S32V234_MSCR_PD7  PAD_CTL_ENET_CFG2
+#define S32V234_PAD_PD8__TX_D1_OUT  S32V234_MSCR_PD8  PAD_CTL_ENET_CFG2
+#define S32V234_PAD_PD9__TX_D2_OUT  S32V234_MSCR_PD9  PAD_CTL_ENET_CFG2
+#define S32V234_PAD_PD10__TX_D3_OUT S32V234_MSCR_PD10 PAD_CTL_ENET_CFG2
+#define S32V234_PAD_PD11__TX_EN_OUT S32V234_MSCR_PD11 PAD_CTL_ENET_CFG2
+
+/* 2D ACE DCU */
+#define S32V234_PAD_PH8__DCU_HSYNC_C1 S32V234_MSCR_PH8  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PH9__DCU_VSYNC_C2 S32V234_MSCR_PH9  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PH10__DCU_DE_C3   S32V234_MSCR_PH10 PAD_CTL_DCU_CFG
+
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_DISABLE S32V234_MSCR_PH12 \
+					PAD_CTL_DCU_CLK_CFG_DSE_DISABLE
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_240     S32V234_MSCR_PH12 \
+					(PAD_CTL_DCU_CLK_CFG_DSE_DISABLE | \
+					PAD_CTL_DSE_240)
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_120     S32V234_MSCR_PH12 \
+					(PAD_CTL_DCU_CLK_CFG_DSE_DISABLE | \
+					PAD_CTL_DSE_120)
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_80      S32V234_MSCR_PH12 \
+					(PAD_CTL_DCU_CLK_CFG_DSE_DISABLE | \
+					PAD_CTL_DSE_80)
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_60      S32V234_MSCR_PH12 \
+					(PAD_CTL_DCU_CLK_CFG_DSE_DISABLE | \
+					PAD_CTL_DSE_60)
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_48      S32V234_MSCR_PH12 \
+					(PAD_CTL_DCU_CLK_CFG_DSE_DISABLE | \
+					PAD_CTL_DSE_48)
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_40      S32V234_MSCR_PH12 \
+					(PAD_CTL_DCU_CLK_CFG_DSE_DISABLE | \
+					PAD_CTL_DSE_40)
+#define S32V234_PAD_PH12__DCU_PCLK_D1_DSE_34      S32V234_MSCR_PH12 \
+					(PAD_CTL_DCU_CLK_CFG_DSE_DISABLE | \
+					PAD_CTL_DSE_34)
+
+#define S32V234_PAD_PH13__DCU_R0_D2  S32V234_MSCR_PH13 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PH14__DCU_R1_D3  S32V234_MSCR_PH14 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PH15__DCU_R2_D4  S32V234_MSCR_PH15 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ0__DCU_R3_D5   S32V234_MSCR_PJ0  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ1__DCU_R4_D6   S32V234_MSCR_PJ1  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ2__DCU_R5_D7   S32V234_MSCR_PJ2  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ3__DCU_R6_D8   S32V234_MSCR_PJ3  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ4__DCU_R7_D9   S32V234_MSCR_PJ4  PAD_CTL_DCU_CFG
+
+#define S32V234_PAD_PJ5__DCU_G0_D10  S32V234_MSCR_PJ5  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ6__DCU_G1_D11  S32V234_MSCR_PJ6  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ7__DCU_G2_D12  S32V234_MSCR_PJ7  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ8__DCU_G3_D13  S32V234_MSCR_PJ8  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ9__DCU_G4_D14  S32V234_MSCR_PJ9  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ10__DCU_G5_D15 S32V234_MSCR_PJ10 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ11__DCU_G6_D16 S32V234_MSCR_PJ11 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ12__DCU_G7_D17 S32V234_MSCR_PJ12 PAD_CTL_DCU_CFG
+
+#define S32V234_PAD_PJ13__DCU_B0_D18 S32V234_MSCR_PJ13 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ14__DCU_B1_D19 S32V234_MSCR_PJ14 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PJ15__DCU_B2_D20 S32V234_MSCR_PJ15 PAD_CTL_DCU_CFG
+#define S32V234_PAD_PK0__DCU_B3_D21  S32V234_MSCR_PK0  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PK1__DCU_B4_D22  S32V234_MSCR_PK1  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PK2__DCU_B5_D23  S32V234_MSCR_PK2  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PK3__DCU_B6_D24  S32V234_MSCR_PK3  PAD_CTL_DCU_CFG
+#define S32V234_PAD_PK4__DCU_B7_D25  S32V234_MSCR_PK4  PAD_CTL_DCU_CFG
+
+/* VIULite0 */
+#define S32V234_PAD_PD13__VIU0_EN    S32V234_MSCR_PD13       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PD13__VIU0_PCLK  S32V234_IMCR_VIU0_PCLK  PAD_CTL_VIU_CFG
+#define S32V234_PAD_PD14__VIU0_EN    S32V234_MSCR_PD14       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PD14__VIU0_HSYNC S32V234_IMCR_VIU0_HSYNC PAD_CTL_VIU_CFG
+#define S32V234_PAD_PD15__VIU0_EN    S32V234_MSCR_PD15       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PD15__VIU0_VSYNC S32V234_IMCR_VIU0_VSYNC PAD_CTL_VIU_CFG
+
+#define S32V234_PAD_PF3__VIU_EN      S32V234_MSCR_PF3        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF3__VIU0_D4     S32V234_IMCR_VIU0_D4    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF4__VIU_EN      S32V234_MSCR_PF4        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF4__VIU0_D5     S32V234_IMCR_VIU0_D5    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF5__VIU_EN      S32V234_MSCR_PF5        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF5__VIU0_D6     S32V234_IMCR_VIU0_D6    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF6__VIU_EN      S32V234_MSCR_PF6        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF6__VIU0_D7     S32V234_IMCR_VIU0_D7    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE0__VIU0_EN     S32V234_MSCR_PE0        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE0__VIU0_D8     S32V234_IMCR_VIU0_D8    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE1__VIU0_EN     S32V234_MSCR_PE1        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE1__VIU0_D9     S32V234_IMCR_VIU0_D9    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE2__VIU0_EN     S32V234_MSCR_PE2        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE2__VIU0_D10    S32V234_IMCR_VIU0_D10   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE3__VIU0_EN     S32V234_MSCR_PE3        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE3__VIU0_D11    S32V234_IMCR_VIU0_D11   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE4__VIU0_EN     S32V234_MSCR_PE4        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE4__VIU0_D12    S32V234_IMCR_VIU0_D12   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE5__VIU0_EN     S32V234_MSCR_PE5        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE5__VIU0_D13    S32V234_IMCR_VIU0_D13   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE6__VIU0_EN     S32V234_MSCR_PE6        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE6__VIU0_D14    S32V234_IMCR_VIU0_D14   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE7__VIU0_EN     S32V234_MSCR_PE7        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE7__VIU0_D15    S32V234_IMCR_VIU0_D15   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE8__VIU0_EN     S32V234_MSCR_PE8        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE8__VIU0_D16    S32V234_IMCR_VIU0_D16   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE9__VIU0_EN     S32V234_MSCR_PE9        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE9__VIU0_D17    S32V234_IMCR_VIU0_D17   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE10__VIU0_EN    S32V234_MSCR_PE10       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE10__VIU0_D18   S32V234_IMCR_VIU0_D18   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE11__VIU0_EN    S32V234_MSCR_PE11       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE11__VIU0_D19   S32V234_IMCR_VIU0_D19   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE12__VIU0_EN    S32V234_MSCR_PE12       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE12__VIU0_D20   S32V234_IMCR_VIU0_D20   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE13__VIU0_EN    S32V234_MSCR_PE13       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE13__VIU0_D21   S32V234_IMCR_VIU0_D21   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE14__VIU0_EN    S32V234_MSCR_PE14       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE14__VIU0_D22   S32V234_IMCR_VIU0_D22   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PE15__VIU0_EN    S32V234_MSCR_PE15       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PE15__VIU0_D23   S32V234_IMCR_VIU0_D23   PAD_CTL_VIU_CFG
+
+/* VIULite1 */
+#define S32V234_PAD_PF0__VIU1_EN    S32V234_MSCR_PF0        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF0__VIU1_PCLK  S32V234_IMCR_VIU1_PCLK  PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF1__VIU1_EN    S32V234_MSCR_PF1        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF1__VIU1_HSYNC S32V234_IMCR_VIU1_HSYNC PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF2__VIU1_EN    S32V234_MSCR_PF2        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF2__VIU1_VSYNC S32V234_IMCR_VIU1_VSYNC PAD_CTL_VIU_CFG
+
+#define S32V234_PAD_PF3__VIU_EN     S32V234_MSCR_PF3        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF3__VIU1_D8    S32V234_IMCR_VIU1_D8    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF4__VIU_EN     S32V234_MSCR_PF4        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF4__VIU1_D9    S32V234_IMCR_VIU1_D9    PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF5__VIU_EN     S32V234_MSCR_PF5        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF5__VIU1_D10   S32V234_IMCR_VIU1_D10   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF6__VIU_EN     S32V234_MSCR_PF6        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF6__VIU1_D11   S32V234_IMCR_VIU1_D11   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF7__VIU1_EN    S32V234_MSCR_PF7        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF7__VIU1_D12   S32V234_IMCR_VIU1_D12   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF8__VIU1_EN    S32V234_MSCR_PF8        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF8__VIU1_D13   S32V234_IMCR_VIU1_D13   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF9__VIU1_EN    S32V234_MSCR_PF9        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF9__VIU1_D14   S32V234_IMCR_VIU1_D14   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF10__VIU1_EN   S32V234_MSCR_PF10       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF10__VIU1_D15  S32V234_IMCR_VIU1_D15   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF11__VIU1_EN   S32V234_MSCR_PF11       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF11__VIU1_D16  S32V234_IMCR_VIU1_D16   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF12__VIU1_EN   S32V234_MSCR_PF12       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF12__VIU1_D17  S32V234_IMCR_VIU1_D17   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF13__VIU1_EN   S32V234_MSCR_PF13       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF13__VIU1_D18  S32V234_IMCR_VIU1_D18   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF14__VIU1_EN   S32V234_MSCR_PF14       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF14__VIU1_D19  S32V234_IMCR_VIU1_D19   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PF15__VIU1_EN   S32V234_MSCR_PF15       PAD_CTL_VIU_IBE
+#define S32V234_PAD_PF15__VIU1_D20  S32V234_IMCR_VIU1_D20   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PG0__VIU1_EN    S32V234_MSCR_PG0        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PG0__VIU1_D21   S32V234_IMCR_VIU1_D21   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PG1__VIU1_EN    S32V234_MSCR_PG1        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PG1__VIU1_D22   S32V234_IMCR_VIU1_D22   PAD_CTL_VIU_CFG
+#define S32V234_PAD_PG2__VIU1_EN    S32V234_MSCR_PG2        PAD_CTL_VIU_IBE
+#define S32V234_PAD_PG2__VIU1_D23   S32V234_IMCR_VIU1_D23   PAD_CTL_VIU_CFG
+
+/* SPI 0-3 */
+#define S32V234_PAD_PB6__SPI0_SOUT_OUT  S32V234_MSCR_PB6 PAD_CTL_SPI_MSCR_SOUT
+#define S32V234_PAD_PB7__SPI0_SIN_OUT   S32V234_MSCR_PB7 PAD_CTL_SPI_MSCR_SIN
+#define S32V234_PAD_PB7__SPI0_SIN_IN    S32V234_IMCR_SPI0_SIN \
+					PAD_CTL_SPI_IMCR_SIN
+#define S32V234_PAD_PB5__SPI0_SCK_OUT   S32V234_MSCR_PB5 PAD_CTL_SPI_MSCR_SCK
+#define S32V234_PAD_PB8__SPI0_CS0_OUT   S32V234_MSCR_PB8 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT1)
+#define S32V234_PAD_PC0__SPI0_CS4_OUT   S32V234_MSCR_PC0 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT3)
+#define S32V234_PAD_PC1__SPI0_CS5_OUT   S32V234_MSCR_PC1 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT3)
+#define S32V234_PAD_PC2__SPI0_CS6_OUT   S32V234_MSCR_PC2 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT3)
+#define S32V234_PAD_PC3__SPI0_CS7_OUT   S32V234_MSCR_PC3 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT2)
+
+#define S32V234_PAD_PB10__SPI1_SOUT_OUT S32V234_MSCR_PB10 PAD_CTL_SPI_MSCR_SOUT
+#define S32V234_PAD_PB11__SPI1_SIN_OUT  S32V234_MSCR_PB11 PAD_CTL_SPI_MSCR_SIN
+#define S32V234_PAD_PB11__SPI1_SIN_IN   S32V234_IMCR_SPI1_SIN \
+					PAD_CTL_SPI_IMCR_SIN
+#define S32V234_PAD_PB9__SPI1_SCK_OUT   S32V234_MSCR_PB9 PAD_CTL_SPI_MSCR_SCK
+#define S32V234_PAD_PB12__SPI1_CS0_OUT  S32V234_MSCR_PB12 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT1)
+
+#define S32V234_PAD_PB14__SPI2_SOUT_OUT S32V234_MSCR_PB14 PAD_CTL_SPI_MSCR_SOUT
+#define S32V234_PAD_PB15__SPI2_SIN_OUT  S32V234_MSCR_PB15 PAD_CTL_SPI_MSCR_SIN
+#define S32V234_PAD_PB15__SPI2_SIN_IN   S32V234_IMCR_SPI2_SIN \
+					PAD_CTL_SPI_IMCR_SIN
+#define S32V234_PAD_P13__SPI2_SCK_OUT   S32V234_MSCR_PB13 PAD_CTL_SPI_MSCR_SCK
+#define S32V234_PAD_PC0__SPI2_CS0_OUT   S32V234_MSCR_PC0 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT1)
+
+#define S32V234_PAD_PC2__SPI3_SOUT_OUT  S32V234_MSCR_PC2 PAD_CTL_SPI_MSCR_SOUT
+#define S32V234_PAD_PC3__SPI3_SIN_OUT   S32V234_MSCR_PC3 PAD_CTL_SPI_MSCR_SIN
+#define S32V234_PAD_PC3__SPI3_SIN_IN    S32V234_IMCR_SPI3_SIN \
+					PAD_CTL_SPI_IMCR_SIN
+#define S32V234_PAD_PC1__SPI3_SCK_OUT   S32V234_MSCR_PC1 PAD_CTL_SPI_MSCR_SCK
+#define S32V234_PAD_PC4__SPI3_CS0_OUT   S32V234_MSCR_PC4 \
+					(PAD_CTL_SPI_MSCR_CSx | \
+					PAD_CTL_MUX_MODE_ALT1)
+
+/* SIUL2 GPIOs */
+#define S32V234_PAD_PA0__SIUL_GPIO0    S32V234_MSCR_PA0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA1__SIUL_GPIO1    S32V234_MSCR_PA1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA2__SIUL_GPIO2    S32V234_MSCR_PA2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA3__SIUL_GPIO3    S32V234_MSCR_PA3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA4__SIUL_GPIO4    S32V234_MSCR_PA4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA5__SIUL_GPIO5    S32V234_MSCR_PA5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA6__SIUL_GPIO6    S32V234_MSCR_PA6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA7__SIUL_GPIO7    S32V234_MSCR_PA7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA8__SIUL_GPIO8    S32V234_MSCR_PA8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA9__SIUL_GPIO9    S32V234_MSCR_PA9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA10__SIUL_GPIO10  S32V234_MSCR_PA10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA11__SIUL_GPIO11  S32V234_MSCR_PA11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA12__SIUL_GPIO12  S32V234_MSCR_PA12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA13__SIUL_GPIO13  S32V234_MSCR_PA13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA14__SIUL_GPIO14  S32V234_MSCR_PA14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PA15__SIUL_GPIO15  S32V234_MSCR_PA15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB0__SIUL_GPIO16   S32V234_MSCR_PB0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB1__SIUL_GPIO17   S32V234_MSCR_PB1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB2__SIUL_GPIO18   S32V234_MSCR_PB2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB3__SIUL_GPIO19   S32V234_MSCR_PB3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB4__SIUL_GPIO20   S32V234_MSCR_PB4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB5__SIUL_GPIO21   S32V234_MSCR_PB5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB6__SIUL_GPIO22   S32V234_MSCR_PB6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB7__SIUL_GPIO23   S32V234_MSCR_PB7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB8__SIUL_GPIO24   S32V234_MSCR_PB8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB9__SIUL_GPIO25   S32V234_MSCR_PB9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB10__SIUL_GPIO26  S32V234_MSCR_PB10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB11__SIUL_GPIO27  S32V234_MSCR_PB11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB12__SIUL_GPIO28  S32V234_MSCR_PB12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB13__SIUL_GPIO29  S32V234_MSCR_PB13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB14__SIUL_GPIO30  S32V234_MSCR_PB14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PB15__SIUL_GPIO31  S32V234_MSCR_PB15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC0__SIUL_GPIO32   S32V234_MSCR_PC0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC1__SIUL_GPIO33   S32V234_MSCR_PC1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC2__SIUL_GPIO34   S32V234_MSCR_PC2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC3__SIUL_GPIO35   S32V234_MSCR_PC3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC4__SIUL_GPIO36   S32V234_MSCR_PC4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC5__SIUL_GPIO37   S32V234_MSCR_PC5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC6__SIUL_GPIO38   S32V234_MSCR_PC6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC7__SIUL_GPIO39   S32V234_MSCR_PC7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC8__SIUL_GPIO40   S32V234_MSCR_PC8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC9__SIUL_GPIO41   S32V234_MSCR_PC9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC10__SIUL_GPIO42  S32V234_MSCR_PC10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC11__SIUL_GPIO43  S32V234_MSCR_PC11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC12__SIUL_GPIO44  S32V234_MSCR_PC12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC13__SIUL_GPIO45  S32V234_MSCR_PC13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC14__SIUL_GPIO46  S32V234_MSCR_PC14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PC15__SIUL_GPIO47  S32V234_MSCR_PC15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD0__SIUL_GPIO48   S32V234_MSCR_PD0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD1__SIUL_GPIO49   S32V234_MSCR_PD1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD2__SIUL_GPIO50   S32V234_MSCR_PD2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD3__SIUL_GPIO51   S32V234_MSCR_PD3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD4__SIUL_GPIO52   S32V234_MSCR_PD4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD5__SIUL_GPIO53   S32V234_MSCR_PD5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD6__SIUL_GPIO54   S32V234_MSCR_PD6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD7__SIUL_GPIO55   S32V234_MSCR_PD7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD8__SIUL_GPIO56   S32V234_MSCR_PD8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD9__SIUL_GPIO57   S32V234_MSCR_PD9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD10__SIUL_GPIO58  S32V234_MSCR_PD10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD11__SIUL_GPIO59  S32V234_MSCR_PD11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD12__SIUL_GPIO60  S32V234_MSCR_PD12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD13__SIUL_GPIO61  S32V234_MSCR_PD13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD14__SIUL_GPIO62  S32V234_MSCR_PD14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PD15__SIUL_GPIO63  S32V234_MSCR_PD15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE0__SIUL_GPIO64   S32V234_MSCR_PE0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE1__SIUL_GPIO65   S32V234_MSCR_PE1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE2__SIUL_GPIO66   S32V234_MSCR_PE2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE3__SIUL_GPIO67   S32V234_MSCR_PE3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE4__SIUL_GPIO68   S32V234_MSCR_PE4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE5__SIUL_GPIO69   S32V234_MSCR_PE5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE6__SIUL_GPIO70   S32V234_MSCR_PE6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE7__SIUL_GPIO71   S32V234_MSCR_PE7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE8__SIUL_GPIO72   S32V234_MSCR_PE8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE9__SIUL_GPIO73   S32V234_MSCR_PE9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE10__SIUL_GPIO74  S32V234_MSCR_PE10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE11__SIUL_GPIO75  S32V234_MSCR_PE11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE12__SIUL_GPIO76  S32V234_MSCR_PE12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE13__SIUL_GPIO77  S32V234_MSCR_PE13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE14__SIUL_GPIO78  S32V234_MSCR_PE14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PE15__SIUL_GPIO79  S32V234_MSCR_PE15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF0__SIUL_GPIO80   S32V234_MSCR_PF0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF1__SIUL_GPIO81   S32V234_MSCR_PF1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF2__SIUL_GPIO82   S32V234_MSCR_PF2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF3__SIUL_GPIO83   S32V234_MSCR_PF3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF4__SIUL_GPIO84   S32V234_MSCR_PF4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF5__SIUL_GPIO85   S32V234_MSCR_PF5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF6__SIUL_GPIO86   S32V234_MSCR_PF6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF7__SIUL_GPIO87   S32V234_MSCR_PF7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF8__SIUL_GPIO88   S32V234_MSCR_PF8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF9__SIUL_GPIO89   S32V234_MSCR_PF9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF10__SIUL_GPIO90  S32V234_MSCR_PF10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF11__SIUL_GPIO91  S32V234_MSCR_PF11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF12__SIUL_GPIO92  S32V234_MSCR_PF12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF13__SIUL_GPIO93  S32V234_MSCR_PF13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF14__SIUL_GPIO94  S32V234_MSCR_PF14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PF15__SIUL_GPIO95  S32V234_MSCR_PF15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG0__SIUL_GPIO96   S32V234_MSCR_PG0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG1__SIUL_GPIO97   S32V234_MSCR_PG1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG2__SIUL_GPIO98   S32V234_MSCR_PG2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG3__SIUL_GPIO99   S32V234_MSCR_PG3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG4__SIUL_GPIO100  S32V234_MSCR_PG4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG5__SIUL_GPIO101  S32V234_MSCR_PG5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG6__SIUL_GPIO102  S32V234_MSCR_PG6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG7__SIUL_GPIO103  S32V234_MSCR_PG7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG8__SIUL_GPIO104  S32V234_MSCR_PG8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG9__SIUL_GPIO105  S32V234_MSCR_PG9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG10__SIUL_GPIO106 S32V234_MSCR_PG10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG11__SIUL_GPIO107 S32V234_MSCR_PG11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG12__SIUL_GPIO108 S32V234_MSCR_PG12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG13__SIUL_GPIO109 S32V234_MSCR_PG13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG14__SIUL_GPIO110 S32V234_MSCR_PG14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PG15__SIUL_GPIO111 S32V234_MSCR_PG15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH0__SIUL_GPIO112  S32V234_MSCR_PH0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH1__SIUL_GPIO113  S32V234_MSCR_PH1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH2__SIUL_GPIO114  S32V234_MSCR_PH2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH3__SIUL_GPIO115  S32V234_MSCR_PH3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH4__SIUL_GPIO116  S32V234_MSCR_PH4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH5__SIUL_GPIO117  S32V234_MSCR_PH5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH6__SIUL_GPIO118  S32V234_MSCR_PH6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH7__SIUL_GPIO119  S32V234_MSCR_PH7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH8__SIUL_GPIO120  S32V234_MSCR_PH8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH9__SIUL_GPIO121  S32V234_MSCR_PH9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH10__SIUL_GPIO122 S32V234_MSCR_PH10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH11__SIUL_GPIO123 S32V234_MSCR_PH11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH12__SIUL_GPIO124 S32V234_MSCR_PH12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH13__SIUL_GPIO125 S32V234_MSCR_PH13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH14__SIUL_GPIO126 S32V234_MSCR_PH14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PH15__SIUL_GPIO127 S32V234_MSCR_PH15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ0__SIUL_GPIO128  S32V234_MSCR_PJ0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ1__SIUL_GPIO129  S32V234_MSCR_PJ1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ2__SIUL_GPIO130  S32V234_MSCR_PJ2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ3__SIUL_GPIO131  S32V234_MSCR_PJ3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ4__SIUL_GPIO132  S32V234_MSCR_PJ4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ5__SIUL_GPIO133  S32V234_MSCR_PJ5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ6__SIUL_GPIO134  S32V234_MSCR_PJ6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ7__SIUL_GPIO135  S32V234_MSCR_PJ7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ8__SIUL_GPIO136  S32V234_MSCR_PJ8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ9__SIUL_GPIO137  S32V234_MSCR_PJ9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ10__SIUL_GPIO138 S32V234_MSCR_PJ10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ11__SIUL_GPIO139 S32V234_MSCR_PJ11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ12__SIUL_GPIO140 S32V234_MSCR_PJ12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ13__SIUL_GPIO141 S32V234_MSCR_PJ13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ14__SIUL_GPIO142 S32V234_MSCR_PJ14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PJ15__SIUL_GPIO143 S32V234_MSCR_PJ15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK0__SIUL_GPIO144  S32V234_MSCR_PK0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK1__SIUL_GPIO145  S32V234_MSCR_PK1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK2__SIUL_GPIO146  S32V234_MSCR_PK2  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK3__SIUL_GPIO147  S32V234_MSCR_PK3  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK4__SIUL_GPIO148  S32V234_MSCR_PK4  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK5__SIUL_GPIO149  S32V234_MSCR_PK5  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK6__SIUL_GPIO150  S32V234_MSCR_PK6  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK7__SIUL_GPIO151  S32V234_MSCR_PK7  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK8__SIUL_GPIO152  S32V234_MSCR_PK8  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK9__SIUL_GPIO153  S32V234_MSCR_PK9  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK10__SIUL_GPIO154 S32V234_MSCR_PK10 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK11__SIUL_GPIO155 S32V234_MSCR_PK11 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK12__SIUL_GPIO156 S32V234_MSCR_PK12 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK13__SIUL_GPIO157 S32V234_MSCR_PK13 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK14__SIUL_GPIO158 S32V234_MSCR_PK14 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PK15__SIUL_GPIO159 S32V234_MSCR_PK15 PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PL0__SIUL_GPIO160  S32V234_MSCR_PL0  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PL1__SIUL_GPIO161  S32V234_MSCR_PL1  PAD_CTL_MUX_MODE_ALT0
+#define S32V234_PAD_PL2__SIUL_GPIO162  S32V234_MSCR_PL2  PAD_CTL_MUX_MODE_ALT0
+
+/* SIUL2 EIRQ pins */
+#define S32V234_PAD_PA0__SIUL_EIRQ0   S32V234_IMCR_SIUL_EIRQ0  PAD_CTL_EIRQ
+#define S32V234_PAD_PA1__SIUL_EIRQ1   S32V234_IMCR_SIUL_EIRQ1  PAD_CTL_EIRQ
+#define S32V234_PAD_PA2__SIUL_EIRQ2   S32V234_IMCR_SIUL_EIRQ2  PAD_CTL_EIRQ
+#define S32V234_PAD_PA3__SIUL_EIRQ3   S32V234_IMCR_SIUL_EIRQ3  PAD_CTL_EIRQ
+#define S32V234_PAD_PA4__SIUL_EIRQ4   S32V234_IMCR_SIUL_EIRQ4  PAD_CTL_EIRQ
+#define S32V234_PAD_PA5__SIUL_EIRQ5   S32V234_IMCR_SIUL_EIRQ5  PAD_CTL_EIRQ
+#define S32V234_PAD_PA6__SIUL_EIRQ6   S32V234_IMCR_SIUL_EIRQ6  PAD_CTL_EIRQ
+#define S32V234_PAD_PA7__SIUL_EIRQ7   S32V234_IMCR_SIUL_EIRQ7  PAD_CTL_EIRQ
+#define S32V234_PAD_PA8__SIUL_EIRQ8   S32V234_IMCR_SIUL_EIRQ8  PAD_CTL_EIRQ
+#define S32V234_PAD_PA9__SIUL_EIRQ9   S32V234_IMCR_SIUL_EIRQ9  PAD_CTL_EIRQ
+#define S32V234_PAD_PA10__SIUL_EIRQ10 S32V234_IMCR_SIUL_EIRQ10 PAD_CTL_EIRQ
+#define S32V234_PAD_PA11__SIUL_EIRQ11 S32V234_IMCR_SIUL_EIRQ11 PAD_CTL_EIRQ
+#define S32V234_PAD_PA12__SIUL_EIRQ12 S32V234_IMCR_SIUL_EIRQ12 PAD_CTL_EIRQ
+#define S32V234_PAD_PA13__SIUL_EIRQ13 S32V234_IMCR_SIUL_EIRQ13 PAD_CTL_EIRQ
+#define S32V234_PAD_PA14__SIUL_EIRQ14 S32V234_IMCR_SIUL_EIRQ14 PAD_CTL_EIRQ
+#define S32V234_PAD_PA15__SIUL_EIRQ15 S32V234_IMCR_SIUL_EIRQ15 PAD_CTL_EIRQ
+#define S32V234_PAD_PB0__SIUL_EIRQ16  S32V234_IMCR_SIUL_EIRQ16 PAD_CTL_EIRQ
+#define S32V234_PAD_PB1__SIUL_EIRQ17  S32V234_IMCR_SIUL_EIRQ17 PAD_CTL_EIRQ
+#define S32V234_PAD_PB2__SIUL_EIRQ18  S32V234_IMCR_SIUL_EIRQ18 PAD_CTL_EIRQ
+#define S32V234_PAD_PB3__SIUL_EIRQ19  S32V234_IMCR_SIUL_EIRQ19 PAD_CTL_EIRQ
+#define S32V234_PAD_PB4__SIUL_EIRQ20  S32V234_IMCR_SIUL_EIRQ20 PAD_CTL_EIRQ
+#define S32V234_PAD_PB5__SIUL_EIRQ21  S32V234_IMCR_SIUL_EIRQ21 PAD_CTL_EIRQ
+#define S32V234_PAD_PB6__SIUL_EIRQ22  S32V234_IMCR_SIUL_EIRQ22 PAD_CTL_EIRQ
+#define S32V234_PAD_PB7__SIUL_EIRQ23  S32V234_IMCR_SIUL_EIRQ23 PAD_CTL_EIRQ
+#define S32V234_PAD_PB8__SIUL_EIRQ24  S32V234_IMCR_SIUL_EIRQ24 PAD_CTL_EIRQ
+#define S32V234_PAD_PB9__SIUL_EIRQ25  S32V234_IMCR_SIUL_EIRQ25 PAD_CTL_EIRQ
+#define S32V234_PAD_PB10__SIUL_EIRQ26 S32V234_IMCR_SIUL_EIRQ26 PAD_CTL_EIRQ
+#define S32V234_PAD_PB11__SIUL_EIRQ27 S32V234_IMCR_SIUL_EIRQ27 PAD_CTL_EIRQ
+#define S32V234_PAD_PB12__SIUL_EIRQ28 S32V234_IMCR_SIUL_EIRQ28 PAD_CTL_EIRQ
+#define S32V234_PAD_PB13__SIUL_EIRQ29 S32V234_IMCR_SIUL_EIRQ29 PAD_CTL_EIRQ
+#define S32V234_PAD_PB14__SIUL_EIRQ30 S32V234_IMCR_SIUL_EIRQ30 PAD_CTL_EIRQ
+#define S32V234_PAD_PB15__SIUL_EIRQ31 S32V234_IMCR_SIUL_EIRQ31 PAD_CTL_EIRQ
+
+#endif /* __DT_BINDINGS_S32V234_PINCTRL_H__ */
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index d40c3b874d81..71ef2acb3c57 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -436,6 +436,15 @@
 #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ			(0x1 << 3)
 #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ			(0x1 << 4)
 
+#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK			(0x1 << 26)
+#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT		(26)
+#define IMX6SX_GPR2_MQS_EN_MASK				(0x1 << 25)
+#define IMX6SX_GPR2_MQS_EN_SHIFT			(25)
+#define IMX6SX_GPR2_MQS_SW_RST_MASK			(0x1 << 24)
+#define IMX6SX_GPR2_MQS_SW_RST_SHIFT			(24)
+#define IMX6SX_GPR2_MQS_CLK_DIV_MASK			(0xFF << 16)
+#define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT			(16)
+
 #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK		(0x1 << 3)
 #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1		(0x0 << 3)
 #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2		(0x1 << 3)