diff options
| author | Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> | 2014-11-28 11:24:14 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-12-01 00:39:58 +0100 |
| commit | 4c1e3ff74d08daf27811112af9f6560c3a6415f1 (patch) | |
| tree | 4cc107b2b742323246d0fb234eec288d6bd2676e | |
| parent | 3db5894beb21df6ee11dfcafc070f1abd4cdf27d (diff) | |
ARM: dts: rockchip: set FIFO size for SDMMC, SDIO and EMMC on rk3066 and rk3188
The SDMMC, SDIO and EMMC controllers use an external FIFO whose size is 256x32bit.
This patch set the corresponding fifo-depth properties for both RK3066 and RK3188.
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm/boot/dts/rk3xxx.dtsi | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 87df6a8955aa..c54a9715dcfa 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -177,10 +177,9 @@ compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; - + fifo-depth = <256>; status = "disabled"; }; @@ -188,10 +187,9 @@ compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; - + fifo-depth = <256>; status = "disabled"; }; @@ -199,10 +197,9 @@ compatible = "rockchip,rk2928-dw-mshc"; reg = <0x1021c000 0x1000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu"; - + fifo-depth = <256>; status = "disabled"; }; |