diff options
| author | Huang Shijie <b32955@freescale.com> | 2011-12-15 11:40:21 +0800 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2012-07-03 16:56:01 -0400 |
| commit | 60ae50d94bd02d3b6dda2bd9afced1eb8427117b (patch) | |
| tree | 172927a58fd47250877d9e2c91dc5b29c881ec8c | |
| parent | f70dbd55315943ab45038deb8a2d2ce043003916 (diff) | |
ENGR00170465-2 MX6Q/UART : enlarge the RX FIFO threthold when DMA is enabled.
Enlarge the RX FIFO threthold from 1 to 16 when the DMA is enabled.
This will give us better performance.
Signed-off-by: Huang Shijie <b32955@freescale.com>
| -rw-r--r-- | drivers/tty/serial/imx.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index f31fa1e16ca7..57988a52f9be 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -136,6 +136,7 @@ #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RXTL_MASK 0x3f /* RX FIFO is 6 bits wide */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ @@ -188,6 +189,8 @@ #define UART_NR 8 +#define UART_RX_SIZE (16) + struct imx_port { struct uart_port port; struct timer_list timer; @@ -596,6 +599,12 @@ static void imx_dma_rxint(struct imx_port *sport) if ((temp & USR2_RDR) && !sport->dma_is_rxing) { sport->dma_is_rxing = true; + /* increase the RX FIFO threthold. */ + temp = readl(sport->port.membase + UFCR); + temp &= ~(UFCR_RXTL_MASK << UFCR_RXTL_SHF); + temp |= UART_RX_SIZE; + writel(temp, sport->port.membase + UFCR); + /* disable the `Recerver Ready Interrrupt` */ temp = readl(sport->port.membase + UCR1); temp &= ~(UCR1_RRDYEN); @@ -781,6 +790,12 @@ static void dma_rx_callback(void *data) temp |= UCR1_RRDYEN; writel(temp, sport->port.membase + UCR1); sport->dma_is_rxing = false; + + /* decrease the RX FIFO threthold. */ + temp = readl(sport->port.membase + UFCR); + temp &= ~(UFCR_RXTL_MASK << UFCR_RXTL_SHF); + temp |= RXTL; + writel(temp, sport->port.membase + UFCR); } } @@ -852,7 +867,7 @@ static int imx_uart_dma_init(struct imx_port *sport) slave_config.direction = DMA_FROM_DEVICE; slave_config.src_addr = sport->port.mapbase + URXD0; slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - slave_config.src_maxburst = RXTL; /* fix me */ + slave_config.src_maxburst = UART_RX_SIZE; ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); if (ret) { pr_err("error in RX dma configuration.\n"); |