serial: 8250: support auto control of RTSCTS on tegra type

Add UART_CAP_HW_CTSRTS flag to tegra type for supporting auto control
of RTSCTS.

Bug 803910

Change-Id: I7b69e4b203e66903ba5755338fcb55f4a87b9a43
Reviewed-on: http://git-master/r/24463
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

3 files changed, 29 insertions, 7 deletions

diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 0243be5bded1..00d304c1ea13 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -313,7 +313,7 @@ static const struct serial8250_config uart_config[] = {
 		.tx_loadsz	= 8,
 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_01 |
 				  UART_FCR_R_TRIG_01,
-		.flags		= UART_CAP_FIFO,
+		.flags		= UART_CAP_FIFO | UART_CAP_HW_CTSRTS,
 	},
 };
 
@@ -1837,8 +1837,13 @@ static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	struct uart_8250_port *up = (struct uart_8250_port *)port;
 	unsigned char mcr = 0;
 
-	if (mctrl & TIOCM_RTS)
-		mcr |= UART_MCR_RTS;
+	if (up->port.type == PORT_TEGRA) {
+		if (mctrl & TIOCM_RTS)
+			mcr |= UART_MCR_HW_RTS;
+	} else {
+		if (mctrl & TIOCM_RTS)
+			mcr |= UART_MCR_RTS;
+	}
 	if (mctrl & TIOCM_DTR)
 		mcr |= UART_MCR_DTR;
 	if (mctrl & TIOCM_OUT1)
@@ -2387,6 +2392,20 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 		serial_outp(up, UART_EFR, efr);
 	}
 
+	if (up->capabilities & UART_CAP_HW_CTSRTS) {
+		unsigned char mcr = serial_inp(up, UART_MCR);
+		/*
+		 * TEGRA UART core support the auto control of the RTS and CTS
+		 * flow control.
+		 */
+		if (termios->c_cflag & CRTSCTS)
+			mcr |= UART_MCR_HW_CTS;
+		else
+			mcr &= ~UART_MCR_HW_CTS;
+		serial_outp(up, UART_MCR, mcr);
+	}
+
+
 #ifdef CONFIG_ARCH_OMAP
 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
 	if (cpu_is_omap1510() && is_omap_port(up)) {
diff --git a/drivers/serial/8250.h b/drivers/serial/8250.h
index 6e19ea3e48d5..4dcd0907fa80 100644
--- a/drivers/serial/8250.h
+++ b/drivers/serial/8250.h
@@ -44,6 +44,7 @@ struct serial8250_config {
 #define UART_CAP_SLEEP	(1 << 10)	/* UART has IER sleep */
 #define UART_CAP_AFE	(1 << 11)	/* MCR-based hw flow control */
 #define UART_CAP_UUE	(1 << 12)	/* UART needs IER bit 6 set (Xscale) */
+#define UART_CAP_HW_CTSRTS	(1 << 13)	/* UART core support hw control of RTS and CTS */
 
 #define UART_BUG_QUOT	(1 << 0)	/* UART has buggy quot LSB */
 #define UART_BUG_TXEN	(1 << 1)	/* UART has buggy TX IIR status */
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index c7a0ce11cd47..0d80447f99be 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -2,10 +2,10 @@
  * include/linux/serial_reg.h
  *
  * Copyright (C) 1992, 1994 by Theodore Ts'o.
- * 
- * Redistribution of this file is permitted under the terms of the GNU 
+ *
+ * Redistribution of this file is permitted under the terms of the GNU
  * Public License (GPL)
- * 
+ *
  * These are the UART port assignments, expressed as offsets from the base
  * register.  These assignments should hold for any serial port based on
  * a 8250, 16450, or 16550(A).
@@ -85,7 +85,7 @@
 
 #define UART_LCR	3	/* Out: Line Control Register */
 /*
- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  */
 #define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
@@ -102,8 +102,10 @@
 #define UART_MCR	4	/* Out: Modem Control Register */
 #define UART_MCR_CLKSEL		0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
 #define UART_MCR_TCRTLR		0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
+#define UART_MCR_HW_RTS 	0x40 /* Enable hw control of RTS (Tegra UART) */
 #define UART_MCR_XONANY		0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
 #define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
+#define UART_MCR_HW_CTS		0x20 /* Enable HW based CTS control (Tegra UART)*/
 #define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
 #define UART_MCR_OUT2		0x08 /* Out2 complement */
 #define UART_MCR_OUT1		0x04 /* Out1 complement */