diff options
| author | Xinyu Chen <b03824@freescale.com> | 2011-08-18 10:23:12 +0800 |
|---|---|---|
| committer | Xinyu Chen <b03824@freescale.com> | 2011-08-18 10:23:12 +0800 |
| commit | 6dee1bc7106cb366562ead7c0983f8975ecc253d (patch) | |
| tree | d1f5ec93517279a78d61df4f280e776599917bb1 | |
| parent | 9fbf48941340e70886abf3e4739fabcedd0a86a8 (diff) | |
Revert "ENGR00154922 [MX6]Disable some clocks during boot"
This reverts commit 187111c874936a35e8d5004db9537d2760f2bae1.
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 34 |
1 files changed, 8 insertions, 26 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 4e1ee83d7a83..1c192b7bee69 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -36,7 +36,6 @@ #define __INIT_CLK_DEBUG(n) #endif -extern int mxc_jtag_enabled; void __iomem *apll_base; static struct clk pll1_sys_main_clk; static struct clk pll2_528_bus_main_clk; @@ -4133,31 +4132,14 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* set the NAND to 11MHz. Too fast will cause dma timeout. */ clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 11000000)); - /* Gate off all possible clocks */ - if (mxc_jtag_enabled) { - __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET | - 3 << MXC_CCM_CCGRx_CG2_OFFSET | - 3 << MXC_CCM_CCGRx_CG1_OFFSET | - 3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0); - } else { - __raw_writel(3 << MXC_CCM_CCGRx_CG2_OFFSET | - 3 << MXC_CCM_CCGRx_CG1_OFFSET | - 3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0); - } - __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1); - __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET | - 3 << MXC_CCM_CCGRx_CG9_OFFSET | - 3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2); - __raw_writel(3 << MXC_CCM_CCGRx_CG14_OFFSET | - 3 << MXC_CCM_CCGRx_CG13_OFFSET | - 3 << MXC_CCM_CCGRx_CG12_OFFSET | - 3 << MXC_CCM_CCGRx_CG11_OFFSET | - 3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3); - __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET | - 3 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4); - __raw_writel(3 << MXC_CCM_CCGRx_CG3_OFFSET | - 3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5); - __raw_writel(0, MXC_CCM_CCGR6); + /* Make sure all clocks are ON initially */ + __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR0); + __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR1); + __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR2); + __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR3); + __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR4); + __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR5); + __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR6); base = ioremap(GPT_BASE_ADDR, SZ_4K); mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); |