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| author | Kefeng Wang <wangkefeng.wang@huawei.com> | 2016-04-08 15:31:50 +0800 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2016-04-27 15:39:54 +0100 |
| commit | 70896650732afd64c410f85c819281dbce8a0974 (patch) | |
| tree | 78d2a4348d00aa1c4162e148b1aaf7b70efde7ae | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff) | |
arm64: dts: hip05: fix its node without msi-cells
Fix commit abf9c25d55e8 ("arm64: dts: hip05: Append all gicv3 ITS
entries"), it forgets the property msi-cell, see arm,gic-v3.txt.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 6319ff3b03ea..52d06ab816db 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -249,24 +249,28 @@ its_peri: interrupt-controller@8c000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0x8c000000 0x0 0x40000>; }; its_m3: interrupt-controller@a3000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xa3000000 0x0 0x40000>; }; its_pcie: interrupt-controller@b7000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xb7000000 0x0 0x40000>; }; its_dsa: interrupt-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xc6000000 0x0 0x40000>; }; }; |