diff options
author | Fugang Duan <fugang.duan@nxp.com> | 2020-04-23 11:43:45 +0800 |
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committer | Fugang Duan <fugang.duan@nxp.com> | 2020-06-16 15:08:02 +0800 |
commit | 890e0a2a6bc233838a5ecfb0946b72b1fcc72061 (patch) | |
tree | 3712c187fa985c3c1ee2d25b426a8bdb74546fcf | |
parent | 0358d500ab7c86b91ba80fe94c4e81dd30ef25c4 (diff) |
MLK-24332 arm64: dts: imx8qm-mek: enable M.2/uSD sdio wlan HIF support
Add M.2/uSD sdio wlan HIF support.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
-rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts | 27 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts | 53 |
3 files changed, 81 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 18c57705c1a5..7997501aa7ba 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \ imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ imx8qm-mek-jdi-wuxga-lvds1-panel-rpmsg.dtb \ + imx8qm-mek-usdhc3-m2.dtb imx8qm-mek-usd-wifi.dtb \ imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \ imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \ imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts new file mode 100644 index 000000000000..4d688997d97a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-usd-wifi.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ +#include "imx8qm-mek-rpmsg.dts" + +&pinctrl_usdhc2 { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000021 + >; +}; + +&usdhc2 { + pinctrl-assert-gpios = <&lsio_gpio4 8 GPIO_ACTIVE_HIGH>; + /delete-property/ cd-gpios; + /delete-property/ wp-gpios; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts new file mode 100644 index 000000000000..a44dd8a2501e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-usdhc3-m2.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ +#include "imx8qm-mek-rpmsg.dts" + +/ { + reg_usdhc3_vmmc: usdhc3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + power-domains = <&pd IMX_SC_R_BOARD_R3>; + }; +}; + +&epdev_on { + regulator-always-on; +}; + +&iomuxc { + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + >; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + pinctrl-assert-gpios = <&lsio_gpio4 10 GPIO_ACTIVE_HIGH>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + cap-power-off-card; + vmmc-supply = <®_usdhc3_vmmc>; + status = "okay"; +}; |