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authorRoland Stigge <stigge@antcom.de>2012-07-01 21:06:45 +0200
committerRoland Stigge <stigge@antcom.de>2012-07-01 21:06:45 +0200
commita0a30b6a69275c54542130a8391e0fda30a4553b (patch)
tree1a2b8ebacdc0a438358481a35a5a8e474da1da86
parentb0d9ef0e2df67685ffc74b1bafa648261ede30c0 (diff)
ARM: LPC32xx: Remove wrong re-initialization of MMC clock register
This patch fixes a bug, (wrongfully) resetting the value of LPC32XX_CLKPWR_MS_CTRL back to its initial contents (after careful setup). This was discovered only with a board/bootloader combination (EA3250) where the contents of the respective register wasn't already at the correct value on Linux boot. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
-rw-r--r--arch/arm/mach-lpc32xx/clock.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index eb1b12092951..b64f98537b5d 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -871,7 +871,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
static int mmc_set_rate(struct clk *clk, unsigned long rate)
{
- u32 oldclk, tmp;
+ u32 tmp;
unsigned long prate, div, crate = mmc_round_rate(clk, rate);
prate = clk->parent->get_rate(clk->parent);
@@ -879,16 +879,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate)
div = prate / crate;
/* The MMC clock must be on when accessing an MMC register */
- oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
- __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
- LPC32XX_CLKPWR_MS_CTRL);
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
- tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
+ tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) |
+ LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
- __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
-
return 0;
}