arm64: dts: imx8: add the fixed hsio ref clocks

External 100Mhz differential OSC is used as HSIO REF clock source, so
set it as the parent clk of the PHY PCLK.
Then add the fixed HSIO REF clocks regarding the different HSIO use
cases.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

4 files changed, 57 insertions, 14 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index a8be49e40c87..830b17940f21 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -13,6 +13,27 @@ hsio_subsys: bus@5f000000 {
 	dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
 	ranges = <0x5f000000 0x0 0x5f000000 0x21000000>;
 
+	xtal100m: clock-xtal100m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "xtal_100MHz";
+	};
+
+	hsio_refa_clk: clock-hsio-refa {
+		compatible = "gpio-gate-clock";
+		clocks = <&xtal100m>;
+		#clock-cells = <0>;
+		enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
+	};
+
+	hsio_refb_clk: clock-hsio-refb {
+		compatible = "gpio-gate-clock";
+		clocks = <&xtal100m>;
+		#clock-cells = <0>;
+		enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
+	};
+
 	hsio_axi_clk: clock-hsio-axi {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -39,20 +60,6 @@ hsio_subsys: bus@5f000000 {
 		power-domains = <&pd IMX_SC_R_PCIE_B>;
 	};
 
-	phyx1_lpcg: clock-controller@5f090000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5f090000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&hsio_per_clk>, <&hsio_per_clk>,
-			<&hsio_per_clk>, <&hsio_per_clk>;
-		bit-offset = <0 4 8 16>;
-		clock-output-names = "hsio_phyx1_pclk",
-				     "hsio_phyx1_epcs_tx_clk",
-				     "hsio_phyx1_epcs_rx_clk",
-				     "hsio_phyx1_apb_clk";
-		power-domains = <&pd IMX_SC_R_SATA_0>;
-	};
-
 	phyx1_crr1_lpcg: clock-controller@5f0b0000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5f0b0000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index c0d4658c24d7..ece43350dadb 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -42,6 +42,20 @@
 		power-domains = <&pd IMX_SC_R_PCIE_A>;
 	};
 
+	phyx1_lpcg: clock-controller@5f090000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5f090000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
+			<&hsio_per_clk>, <&hsio_per_clk>;
+		bit-offset = <0 4 8 16>;
+		clock-output-names = "hsio_phyx1_pclk",
+				     "hsio_phyx1_epcs_tx_clk",
+				     "hsio_phyx1_epcs_rx_clk",
+				     "hsio_phyx1_apb_clk";
+		power-domains = <&pd IMX_SC_R_SERDES_1>;
+	};
+
 	phyx2_crr0_lpcg: clock-controller@5f0a0000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5f0a0000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi
new file mode 100644
index 000000000000..4fae19e5edb4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *	Richard Zhu <hongxing.zhu@nxp.com>
+ */
+
+&hsio_subsys {
+	phyx1_lpcg: clock-controller@5f090000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5f090000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
+			<&hsio_per_clk>, <&hsio_per_clk>;
+		bit-offset = <0 4 8 16>;
+		clock-output-names = "hsio_phyx1_pclk",
+				     "hsio_phyx1_epcs_tx_clk",
+				     "hsio_phyx1_epcs_rx_clk",
+				     "hsio_phyx1_apb_clk";
+		power-domains = <&pd IMX_SC_R_SERDES_1>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4c77ea466c7a..3ee4dca8d947 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -336,6 +336,7 @@
 #include "imx8qxp-ss-adma.dtsi"
 #include "imx8qxp-ss-conn.dtsi"
 #include "imx8qxp-ss-lsio.dtsi"
+#include "imx8qxp-ss-hsio.dtsi"
 #include "imx8qxp-ss-dc.dtsi"
 #include "imx8qxp-ss-lvds.dtsi"