diff options
| author | Nitin Garg <nitin.garg@freescale.com> | 2012-05-14 12:54:42 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2012-05-14 12:55:39 -0500 |
| commit | b27ee593a5e3d898853570f233f1bfbbfdad2e4f (patch) | |
| tree | 059bbfde12018153238695305157ed59437147d8 | |
| parent | d63c1504d9e5626f1b29d8d603356c63b80b1e85 (diff) | |
ENGR00181752: Linux-3.0 porting to iMX53 SMD platform
This is the initial Linux-3.0 kernel porting to iMX53 SMD
platform.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
92 files changed, 6517 insertions, 1193 deletions
diff --git a/arch/arm/configs/imx5_android_defconfig b/arch/arm/configs/imx5_android_defconfig new file mode 100644 index 000000000000..1e3afef8baab --- /dev/null +++ b/arch/arm/configs/imx5_android_defconfig @@ -0,0 +1,2913 @@ +# +# Automatically generated make config: don't edit +# Linux/arm 3.0.15 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_SCHED_CLOCK=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_FIQ=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +# CONFIG_TREE_PREEMPT_RCU is not set +CONFIG_TINY_RCU=y +# CONFIG_TINY_PREEMPT_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +# CONFIG_CGROUP_MEM_RES_CTLR is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +# CONFIG_NAMESPACES is not set +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_PANIC_TIMEOUT=0 +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_ASHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_THROTTLING is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_CFQ_GROUP_IOSCHED is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS4 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_IMX_HAVE_PLATFORM_FEC=y +CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y +CONFIG_IMX_HAVE_PLATFORM_IMX_SRTC=y +CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y +CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y +CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y +CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y +CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y +CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y +CONFIG_IMX_HAVE_PLATFORM_IMX_TVE=y +CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y +CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y +CONFIG_IMX_HAVE_PLATFORM_AHCI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_IIM=y +CONFIG_IMX_HAVE_PLATFORM_MXC_GPU=y +CONFIG_IMX_HAVE_PLATFORM_LDB=y +CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y +CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y + +# +# Freescale MXC Implementations +# +CONFIG_ARCH_MX50_SUPPORTED=y +CONFIG_ARCH_MX53_SUPPORTED=y +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX3 is not set +CONFIG_ARCH_MX503=y +# CONFIG_ARCH_MX51 is not set +# CONFIG_ARCH_MX6 is not set +CONFIG_ARCH_MX5=y +CONFIG_ARCH_MX53=y +CONFIG_SOC_IMX53=y +CONFIG_FORCE_MAX_ZONEORDER=13 +# CONFIG_MACH_MX50_RDP is not set + +# +# i.MX53 machines: +# +# CONFIG_MACH_MX53_EVK is not set +CONFIG_MACH_MX53_SMD=y +# CONFIG_MACH_MX53_LOCO is not set +# CONFIG_MACH_MX53_ARD is not set +CONFIG_MACH_IMX_BLUETOOTH_RFKILL=y +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_TZIC=y +CONFIG_MXC_PWM=y +CONFIG_MXC_DEBUG_BOARD=y +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_ARCH_MXC_AUDMUX_V2=y +CONFIG_IRAM_ALLOC=y +CONFIG_CLK_DEBUG=y +CONFIG_DMA_ZONE_SIZE=16 + +# +# System MMU +# + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_FIQ_DEBUGGER is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttymxc0,115200 init=/init androidboot.console=ttymxc0 video=mxcdi1fb:RGB666,LDB-XGA ldb=di1 di1_primary pmem=128M,64M fbmem=10M gpu_memory=128M vmalloc=576M" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_SUSPEND=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HAS_WAKELOCK=y +CONFIG_HAS_EARLYSUSPEND=y +# CONFIG_CPUFREQ_GOV_ON_EARLYSUPSEND is not set +CONFIG_WAKELOCK=y +CONFIG_WAKELOCK_STAT=y +CONFIG_USER_WAKELOCK=y +CONFIG_EARLYSUSPEND=y +# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set +# CONFIG_CONSOLE_EARLYSUSPEND is not set +CONFIG_FB_EARLYSUSPEND=y +CONFIG_PM_SLEEP=y +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_APM_EMULATION=y +CONFIG_PM_RUNTIME_CLK=y +# CONFIG_SUSPEND_TIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +# CONFIG_IPV6_ROUTE_INFO is not set +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +CONFIG_ANDROID_PARANOID_NETWORK=y +CONFIG_NET_ACTIVITY_STATS=y +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_BROADCAST=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +CONFIG_NETFILTER_XT_TARGET_MARK=y +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_HL=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +# CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_REJECT_SKERR is not set +CONFIG_IP_NF_TARGET_LOG=y +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_NF_NAT_SNMP_BASIC=y +CONFIG_NF_NAT_PROTO_DCCP=y +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_PROTO_UDPLITE=y +CONFIG_NF_NAT_PROTO_SCTP=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=y +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_AMANDA=y +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +CONFIG_NF_NAT_SIP=y +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=y +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=y +# CONFIG_NF_CONNTRACK_IPV6 is not set +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +# CONFIG_IP6_NF_TARGET_REJECT_SKERR is not set +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +# CONFIG_IP6_NF_SECURITY is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_PHONET=y +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=y +# CONFIG_CAN_SLCAN is not set +# CONFIG_CAN_DEV is not set +CONFIG_CAN_DEBUG_DEVICES=y +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +# CONFIG_BT_HCIUART_H4 is not set +# CONFIG_BT_HCIUART_BCSP is not set +CONFIG_BT_HCIUART_ATH3K=y +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +CONFIG_BT_HCIVHCI=y +# CONFIG_BT_MRVL is not set +# CONFIG_BT_ATH3K is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_CFG80211_ALLOW_RECONNECT is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_PM=y +CONFIG_RFKILL_INPUT=y +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +CONFIG_ANDROID_PMEM=y +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_SUSPEND_COUNTER is not set +# CONFIG_HMC6352 is not set +# CONFIG_SENSORS_AK8975 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_UID_STAT=y +# CONFIG_BMP085 is not set +# CONFIG_WL127X_RFKILL is not set +# CONFIG_APANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_MII is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_FEC=y +CONFIG_FEC_NAPI=y +# CONFIG_FEC_1588 is not set +# CONFIG_FTMAC100 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_WIFI_CONTROL_FUNC is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_ATH6KL_DEBUG is not set +# CONFIG_BCM4329 is not set +# CONFIG_BCMDHD is not set +CONFIG_HOSTAP=y +# CONFIG_HOSTAP_FIRMWARE is not set +# CONFIG_IWM is not set +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_CDC_PHONET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set + +# +# CAIF transport drivers +# +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +# CONFIG_PPP_MPPE is not set +CONFIG_PPPOE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set +# CONFIG_INPUT_KEYRESET is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_MXC is not set +CONFIG_KEYBOARD_MPR121=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +CONFIG_TOUCHSCREEN_EGALAX=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +CONFIG_TOUCHSCREEN_MAX11801=y +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_MC13783 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +CONFIG_TOUCHSCREEN_P1003=y +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_DA9052 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +CONFIG_INPUT_KEYCHORD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_GPIO is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set +CONFIG_INPUT_DA9052_ONKEY=y +CONFIG_INPUT_ISL29023=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DCC_TTY is not set +# CONFIG_RAMOOPS is not set +CONFIG_MXC_IIM=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_IMX_VER_0_7=y +CONFIG_SPI_IMX_VER_2_3=y +CONFIG_SPI_IMX=y +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_BASIC_MMIO is not set +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_DA9052_GPIO_ENABLE is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_APM_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ20Z75 is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_BATTERY_MAX17085=y +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_BATTERY_DA9052 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +CONFIG_SENSORS_DA9052=y +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +CONFIG_SENSORS_MAX17135=y +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_MC13783_ADC is not set +CONFIG_SENSORS_IMX_AHCI=y +CONFIG_SENSORS_MAG3110=y +CONFIG_MXC_MMA8450=y +CONFIG_MXC_MMA8451=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_IMX2_WDT=y +# CONFIG_DA9052_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set +CONFIG_MFD_SUPPORT=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +CONFIG_PMIC_DIALOG=y +CONFIG_PMIC_DA9052=y +# CONFIG_PMIC_DA9053AA is not set +# CONFIG_PMIC_DA9053Bx is not set +CONFIG_MFD_MC_PMIC=y +CONFIG_MFD_MC34708=y +# CONFIG_MFD_PFUZE is not set +CONFIG_MFD_MC13783=y +CONFIG_MFD_MC13XXX=y +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65910 is not set +CONFIG_MFD_MAX17135=y +CONFIG_MFD_MXC_HDMI=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +CONFIG_REGULATOR_MC13XXX_CORE=y +# CONFIG_REGULATOR_MC13783 is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_MC34708=y +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_DA9052=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_MEDIA_CONTROLLER is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_CUSTOMISE=y + +# +# Customize TV tuners +# +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +CONFIG_MEDIA_TUNER_MAX2165=m +# CONFIG_MEDIA_TUNER_TDA18218 is not set +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +CONFIG_VIDEO_MXC_CAMERA=y + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_IPU_CAMERA=y +# CONFIG_VIDEO_MXC_CSI_CAMERA is not set +# CONFIG_MXC_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640 is not set +# CONFIG_MXC_CAMERA_OV3640 is not set +# CONFIG_MXC_CAMERA_OV5640 is not set +CONFIG_MXC_CAMERA_OV5642=y +CONFIG_MXC_CAMERA_SENSOR_CLK=y +CONFIG_MXC_IPU_PRP_VF_SDC=y +CONFIG_MXC_IPU_PRP_ENC=y +CONFIG_MXC_IPU_CSI_ENC=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_GSPCA is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_ION is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_DA9052 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +CONFIG_FB_MXC=y +CONFIG_FB_MXC_EDID=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +CONFIG_FB_MXC_TVOUT_TVE=y +CONFIG_FB_MXC_LDB=y +# CONFIG_FB_MXC_MIPI_DSI is not set +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set +CONFIG_FB_MXC_SII902X=y +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +# CONFIG_FB_MXC_EINK_PANEL is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_MXC_HDMI is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_SOC=y +# CONFIG_SND_SOC_CACHE_LZO is not set +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_MXC_SOC_MX2=y +CONFIG_SND_MXC_SOC_SPDIF_DAI=y +CONFIG_SND_SOC_IMX_SGTL5000=y +# CONFIG_SND_SOC_IMX_WM8962 is not set +# CONFIG_SND_SOC_IMX_CS42888 is not set +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_MXC_HDMI=y +CONFIG_SND_SOC_MXC_SPDIF=y +CONFIG_SND_SOC_SGTL5000=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_ARVO is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_ROCCAT_KONEPLUS is not set +# CONFIG_HID_ROCCAT_KOVAPLUS is not set +# CONFIG_HID_ROCCAT_PYRA is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_MXC is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_WWAN=y +CONFIG_USB_SERIAL_OPTION=y +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_GADGET_SELECTED=y +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_FUSB300 is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA_U2O is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_G_ANDROID=y +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_OTG_WAKELOCK is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MXC_OTG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_EMBEDDED_SDIO is not set +# CONFIG_MMC_PARANOID_SD_INIT is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +CONFIG_SDHCI_USE_LEDS_CLASS=y +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_MC13783 is not set +# CONFIG_LEDS_TRIGGERS is not set + +# +# LED Triggers +# +# CONFIG_LEDS_DA9052 is not set + +# +# LED Triggers +# +# CONFIG_NFC_DEVICES is not set +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_INTF_ALARM=y +CONFIG_RTC_INTF_ALARM_DEV=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_MC34708=y +CONFIG_RTC_DRV_DA9052=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +# CONFIG_DW_DMAC is not set +# CONFIG_TIMB_DMA is not set +CONFIG_IMX_SDMA=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +CONFIG_STAGING=y +# CONFIG_USBIP_CORE is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_ECHO is not set +# CONFIG_BRCMUTIL is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_R8712U is not set +# CONFIG_TRANZPORT is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +# CONFIG_ANDROID_RAM_CONSOLE is not set +# CONFIG_ANDROID_TIMED_OUTPUT is not set +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +# CONFIG_POHMELFS is not set +# CONFIG_LINE6_USB is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# CONFIG_VT6656 is not set +# CONFIG_IIO is not set +# CONFIG_XVMALLOC is not set +# CONFIG_ZRAM is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_EASYCAP is not set +CONFIG_MACH_NO_WESTBRIDGE=y +CONFIG_ATH6K_LEGACY=m +CONFIG_AR600x_SD31_XXX=y +# CONFIG_AR600x_WB31_XXX is not set +# CONFIG_AR600x_SD32_XXX is not set +# CONFIG_AR600x_CUSTOM_XXX is not set +# CONFIG_ATH6KL_ENABLE_COEXISTENCE is not set +# CONFIG_ATH6KL_HCI_BRIDGE is not set +# CONFIG_ATH6KL_HTC_RAW_INTERFACE is not set +# CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER is not set +# CONFIG_ATH6KL_SKIP_ABI_VERSION_CHECK is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y +CONFIG_MXC_IPU_V3EX=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_I2C=y +CONFIG_MXC_PMIC_SPI=y +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +CONFIG_MXC_MC13892_RTC=y +CONFIG_MXC_MC13892_LIGHT=y +CONFIG_MXC_MC13892_BATTERY=m +CONFIG_MXC_MC13892_CONNECTIVITY=y +CONFIG_MXC_MC13892_POWER=y +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_SCC2 is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# SAHARA2 Security Hardware Support +# +# CONFIG_MXC_SAHARA is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# +CONFIG_MXC_ASRC=y + +# +# MXC Bluetooth support +# + +# +# Broadcom GPS ioctrl support +# + +# +# MXC Media Local Bus Driver +# +# CONFIG_MXC_MLB50 is not set + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC AMD GPU support +# +CONFIG_MXC_AMD_GPU=y + +# +# ANATOP_THERMAL +# + +# +# MXC MIPI Support +# + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SPARSE_RCU_POINTER is not set +CONFIG_STACKTRACE=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_LKDTM is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set +# CONFIG_SECURITY_PATH is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_IMA is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_CRYPTODEV=y + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=y +CONFIG_TEXTSEARCH_BM=y +CONFIG_TEXTSEARCH_FSM=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_AVERAGE=y diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index acac8d329e4a..60297a17321e 100755 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -48,6 +48,7 @@ config SOC_IMX53 select ARM_L1_CACHE_SHIFT_6 select MXC_TZIC select ARCH_MXC_IOMUX_V3 + select ARCH_MXC_AUDMUX_V2 select ARCH_MX5 select ARCH_MX53 select ARCH_HAS_CPUFREQ @@ -63,6 +64,10 @@ config SOC_IMX53 select IMX_HAVE_PLATFORM_IMX_SPDIF select IMX_HAVE_PLATFORM_IMX_ESAI +config FORCE_MAX_ZONEORDER + int "MAX_ORDER" + default "13" + if ARCH_MX50_SUPPORTED #comment "i.MX50 machines:" @@ -223,6 +228,8 @@ config MACH_MX53_SMD select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_IMX_SRTC select IMX_HAVE_PLATFORM_AHCI + select IMX_HAVE_PLATFORM_SPI_IMX + select IMX_HAVE_PLATFORM_IMX_ASRC help Include support for MX53 SMD platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 8dbcf863f42e..eb99bf7db625 100755 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -4,17 +4,17 @@ # Object file lists. obj-y := cpu.o mm.o devices.o ehci.o bus_freq.o sdram_autogating.o \ -pm.o system.o suspend.o usb_dr.o usb_h1.o usb_h2.o cpu_regulator-mx5.o +pm.o system.o suspend.o usb_dr.o usb_h1.o usb_h2.o cpu_regulator-mx5.o check_fuse.o obj-$(CONFIG_SOC_IMX50) += clock_mx50.o mm-mx50.o mx50_wfi.o mx50_suspend.o mx50_freq.o mx50_ddr_freq.o obj-$(CONFIG_SOC_IMX51) += clock.o obj-$(CONFIG_SOC_IMX53) += clock.o -obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o cpu_op-mx53.o cpu_op-mx50.o +obj-$(CONFIG_SOC_IMX53) += cpu_op-mx51.o cpu_op-mx53.o cpu_op-mx50.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o mx51_babbage_pmic_mc13892.o obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o -obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o mx53_smd_pmic_da9053.o +obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o pm_i2c.o pm_da9053.o mx53_smd_pmic_da9053.o obj-$(CONFIG_MACH_IMX_BLUETOOTH_RFKILL) += imx_bt_rfkill.o obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o mx53_loco_pmic_da9053.o mx53_loco_pmic_mc34708.o obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o diff --git a/arch/arm/mach-mx5/android.h b/arch/arm/mach-mx5/android.h new file mode 100644 index 000000000000..c95c75c094d9 --- /dev/null +++ b/arch/arm/mach-mx5/android.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef ANDROID_H +#define ANDROID_H + +extern struct platform_device mxc_android_pmem_device; +extern struct platform_device mxc_android_pmem_gpu_device; + +#endif diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 50fec0737b36..249cea44bfa5 100755 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -28,16 +28,18 @@ #include <linux/fsl_devices.h> #include <linux/ahci_platform.h> #include <linux/regulator/consumer.h> - +#include <linux/android_pmem.h> #include <linux/pwm_backlight.h> #include <linux/mxcfb.h> #include <linux/ipu.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> +#include <linux/mfd/da9052/da9052.h> #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> #include <linux/mtd/partitions.h> +#include <linux/memblock.h> #include <mach/common.h> #include <mach/hardware.h> @@ -46,147 +48,204 @@ #include <mach/iomux-mx53.h> #include <mach/ahci_sata.h> #include <mach/imx_rfkill.h> +#include <mach/mxc_asrc.h> +#include <mach/mxc_dvfs.h> +#include <mach/check_fuse.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> +#include <asm/setup.h> #include "crm_regs.h" #include "devices-imx53.h" #include "devices.h" #include "usb.h" +#include "android.h" +#include "pmic.h" +/* MX53 SMD GPIO PIN configurations */ +#define MX53_SMD_KEY_RESET IMX_GPIO_NR(1, 2) +#define MX53_SMD_SATA_CLK_GPEN IMX_GPIO_NR(1, 4) +#define MX53_SMD_PMIC_FAULT IMX_GPIO_NR(1, 5) +#define MX53_SMD_SYS_ON_OFF_CTL IMX_GPIO_NR(1, 7) +#define MX53_SMD_PMIC_ON_OFF_REQ IMX_GPIO_NR(1, 8) -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_SMD_FEC_INT IMX_GPIO_NR(2, 4) +#define MX53_SMD_HEADPHONE_DEC IMX_GPIO_NR(2, 5) +#define MX53_SMD_ZIGBEE_INT IMX_GPIO_NR(2, 6) +#define MX53_SMD_ZIGBEE_RESET_B IMX_GPIO_NR(2, 7) +#define MX53_SMD_GPS_RESET_B IMX_GPIO_NR(2, 12) +#define MX53_SMD_WAKEUP_ZIGBEE IMX_GPIO_NR(2, 13) +#define MX53_SMD_UI2 IMX_GPIO_NR(2, 14) +#define MX53_SMD_UI1 IMX_GPIO_NR(2, 15) +#define MX53_SMD_FEC_PWR_EN IMX_GPIO_NR(2, 16) +#define MX53_SMD_LID_OPN_CLS_SW IMX_GPIO_NR(2, 23) +#define MX53_SMD_GPS_PPS IMX_GPIO_NR(2, 24) +#define MX53_SMD_ECSPI1_CS0 IMX_GPIO_NR(2, 30) + +#define MX53_SMD_DCDC1V8_EN IMX_GPIO_NR(3, 1) +#define MX53_SMD_AUD_AMP_STBY_B IMX_GPIO_NR(3, 2) +#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) +#define MX53_SMD_TPM_OSC_EN IMX_GPIO_NR(3, 4) +#define MX53_SMD_WLAN_PD IMX_GPIO_NR(3, 5) +#define MX53_SMD_WiFi_BT_PWR_EN IMX_GPIO_NR(3, 10) +#define MX53_SMD_RECOVERY_MODE_SW IMX_GPIO_NR(3, 11) +#define MX53_SMD_USB_OTG_OC IMX_GPIO_NR(3, 12) #define MX53_SMD_SD1_CD IMX_GPIO_NR(3, 13) +#define MX53_SMD_USB_HUB_RESET_B IMX_GPIO_NR(3, 14) +#define MX53_SMD_eCOMPASS_INT IMX_GPIO_NR(3, 15) +#define MX53_SMD_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#define MX53_SMD_CAP_TCH_INT1 IMX_GPIO_NR(3, 20) +#define MX53_SMD_BT_PRIORITY IMX_GPIO_NR(3, 21) +#define MX53_SMD_ALS_INT IMX_GPIO_NR(3, 22) +#define MX53_SMD_TPM_INT IMX_GPIO_NR(3, 26) +#define MX53_SMD_MODEM_WKUP IMX_GPIO_NR(3, 27) +#define MX53_SMD_BT_RESET IMX_GPIO_NR(3, 28) +#define MX53_SMD_TPM_RST_B IMX_GPIO_NR(3, 29) +#define MX53_SMD_CHRG_OR_CMOS IMX_GPIO_NR(3, 30) +#define MX53_SMD_CAP_TCH_INT0 IMX_GPIO_NR(3, 31) + +#define MX53_SMD_MODEM_DISABLE_B IMX_GPIO_NR(4, 10) #define MX53_SMD_SD1_WP IMX_GPIO_NR(4, 11) +#define MX53_SMD_DCDC5V_BB_EN IMX_GPIO_NR(4, 14) +#define MX53_SMD_WLAN_HOST_WAKE IMX_GPIO_NR(4, 15) + #define MX53_SMD_HDMI_RESET_B IMX_GPIO_NR(5, 0) #define MX53_SMD_MODEM_RESET_B IMX_GPIO_NR(5, 2) #define MX53_SMD_KEY_INT IMX_GPIO_NR(5, 4) -#define MX53_SMD_HDMI_INT IMX_GPIO_NR(6, 12) -#define MX53_SMD_CAP_TCH_INT1 IMX_GPIO_NR(3, 20) -#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) -#define MX53_SMD_OTG_VBUS IMX_GPIO_NR(7, 8) -#define MX53_SMD_NONKEY IMX_GPIO_NR(1, 8) -#define MX53_SMD_UI1 IMX_GPIO_NR(2, 14) -#define MX53_SMD_UI2 IMX_GPIO_NR(2, 15) -#define MX53_SMD_HEADPHONE_DEC IMX_GPIO_NR(2, 5) -#define MX53_SMD_OSC_CKIH1_EN IMX_GPIO_NR(6, 11) -#define MX53_SMD_DCDC1V8_EN IMX_GPIO_NR(3, 1) -#define MX53_SMD_DCDC5V_BB_EN IMX_GPIO_NR(4, 14) -#define MX53_SMD_ALS_INT IMX_GPIO_NR(3, 22) -#define MX53_SMD_BT_RESET IMX_GPIO_NR(3, 28) + +#define MX53_SMD_CAP_TCH_FUN0 IMX_GPIO_NR(6, 6) #define MX53_SMD_CSI0_RST IMX_GPIO_NR(6, 9) #define MX53_SMD_CSI0_PWN IMX_GPIO_NR(6, 10) -#define MX53_SMD_ECSPI1_CS0 IMX_GPIO_NR(2, 30) -#define MX53_SMD_ECSPI1_CS1 IMX_GPIO_NR(3, 19) - +#define MX53_SMD_OSC_CKIH1_EN IMX_GPIO_NR(6, 11) +#define MX53_SMD_HDMI_INT IMX_GPIO_NR(6, 12) +#define MX53_SMD_LCD_PWR_EN IMX_GPIO_NR(6, 13) +#define MX53_SMD_ACCL_INT1_IN IMX_GPIO_NR(6, 15) +#define MX53_SMD_ACCL_INT2_IN IMX_GPIO_NR(6, 16) +#define MX53_SMD_AC_IN IMX_GPIO_NR(6, 17) +#define MX53_SMD_PWR_GOOD IMX_GPIO_NR(6, 18) + +#define MX53_SMD_CABC_EN0 IMX_GPIO_NR(7, 2) +#define MX53_SMD_DOCK_DECTECT IMX_GPIO_NR(7, 3) +#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_SMD_USER_DEG_CHG_NONE IMX_GPIO_NR(7, 7) +#define MX53_SMD_OTG_VBUS IMX_GPIO_NR(7, 8) +#define MX53_SMD_DEVELOP_MODE_SW IMX_GPIO_NR(7, 9) +#define MX53_SMD_CABC_EN1 IMX_GPIO_NR(7, 10) +#define MX53_SMD_PMIC_INT IMX_GPIO_NR(7, 11) +#define MX53_SMD_CAP_TCH_FUN1 IMX_GPIO_NR(7, 13) + +#define TZIC_WAKEUP0_OFFSET 0x0E00 +#define TZIC_WAKEUP1_OFFSET 0x0E04 +#define TZIC_WAKEUP2_OFFSET 0x0E08 +#define TZIC_WAKEUP3_OFFSET 0x0E0C +#define GPIO7_0_11_IRQ_BIT (0x1<<11) + +void __init early_console_setup(unsigned long base, struct clk *clk); static struct clk *sata_clk, *sata_ref_clk; +static int fs_in_sdcard; extern char *lp_reg_id; extern char *gp_reg_id; extern void mx5_cpu_regulator_init(void); extern int mx53_smd_init_da9052(void); -extern void mx5_cpu_regulator_init(void); static iomux_v3_cfg_t mx53_smd_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* I2C2 */ - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* I2C3 */ - MX53_PAD_GPIO_3__I2C3_SCL, - MX53_PAD_GPIO_6__I2C3_SDA, - + /* DI_VGA_HSYNC */ + MX53_PAD_EIM_OE__IPU_DI1_PIN7, + /* HDMI reset */ + MX53_PAD_EIM_WAIT__GPIO5_0, + /* DI_VGA_VSYNC */ + MX53_PAD_EIM_RW__IPU_DI1_PIN8, /* CSPI1 */ MX53_PAD_EIM_EB2__ECSPI1_SS0, MX53_PAD_EIM_D16__ECSPI1_SCLK, MX53_PAD_EIM_D17__ECSPI1_MISO, MX53_PAD_EIM_D18__ECSPI1_MOSI, MX53_PAD_EIM_D19__ECSPI1_SS1, - MX53_PAD_EIM_EB2__GPIO2_30, - MX53_PAD_EIM_D19__GPIO3_19, - - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1_CD */ - MX53_PAD_EIM_DA13__GPIO3_13, - /* SD1_WP */ - MX53_PAD_KEY_ROW2__GPIO4_11, - - /* SD2 */ - MX53_PAD_SD2_CMD__ESDHC2_CMD, - MX53_PAD_SD2_CLK__ESDHC2_CLK, - MX53_PAD_SD2_DATA0__ESDHC2_DAT0, - MX53_PAD_SD2_DATA1__ESDHC2_DAT1, - MX53_PAD_SD2_DATA2__ESDHC2_DAT2, - MX53_PAD_SD2_DATA3__ESDHC2_DAT3, - - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - + /* BT: UART3*/ + MX53_PAD_EIM_D24__UART3_TXD_MUX, + MX53_PAD_EIM_D25__UART3_RXD_MUX, + MX53_PAD_EIM_EB3__UART3_RTS, + MX53_PAD_EIM_D23__UART3_CTS, + /* LID_OPN_CLS_SW*/ + MX53_PAD_EIM_CS0__GPIO2_23, + /* GPS_PPS */ + MX53_PAD_EIM_CS1__GPIO2_24, + /* FEC_PWR_EN */ + MX53_PAD_EIM_A22__GPIO2_16, + /* CAP_TCH_FUN0*/ + MX53_PAD_EIM_A23__GPIO6_6, + /* KEY_INT */ + MX53_PAD_EIM_A24__GPIO5_4, + /* MODEM_RESET_B */ + MX53_PAD_EIM_A25__GPIO5_2, + /* CAP_TCH_INT1 */ + MX53_PAD_EIM_D20__GPIO3_20, + /* BT_PRIORITY */ + MX53_PAD_EIM_D21__GPIO3_21, + /* ALS_INT */ + MX53_PAD_EIM_D22__GPIO3_22, + /* TPM_INT */ + MX53_PAD_EIM_D26__GPIO3_26, + /* MODEM_WKUP */ + MX53_PAD_EIM_D27__GPIO3_27, + /* BT_RESET */ + MX53_PAD_EIM_D28__GPIO3_28, + /* TPM_RST_B */ + MX53_PAD_EIM_D29__GPIO3_29, + /* CHARGER_NOW_OR_CMOS_RUN */ + MX53_PAD_EIM_D30__GPIO3_30, + /* CAP_TCH_INT0 */ + MX53_PAD_EIM_D31__GPIO3_31, + /* DCDC1V8_EN */ + MX53_PAD_EIM_DA1__GPIO3_1, + /* AUD_AMP_STBY_B */ + MX53_PAD_EIM_DA2__GPIO3_2, /* SATA_PWR_EN */ MX53_PAD_EIM_DA3__GPIO3_3, - + /* TPM_OSC_EN */ + MX53_PAD_EIM_DA4__GPIO3_4, + /* WLAN_PD */ + MX53_PAD_EIM_DA5__GPIO3_5, + /* WiFi_BT_PWR_EN */ + MX53_PAD_EIM_DA10__GPIO3_10, + /* RECOVERY_MODE_SW */ + MX53_PAD_EIM_DA11__GPIO3_11, /* USB_OTG_OC */ MX53_PAD_EIM_DA12__GPIO3_12, + /* SD1_CD */ + MX53_PAD_EIM_DA13__GPIO3_13, /* USB_HUB_RESET_B */ MX53_PAD_EIM_DA14__GPIO3_14, - /* USB_OTG_PWR_EN */ - MX53_PAD_PATA_DA_2__GPIO7_8, - - /* OSC_CKIH1_EN, for audio codec clk */ + /* eCOMPASS_IN */ + MX53_PAD_EIM_DA15__GPIO3_15, + /* HDMI_INT */ + MX53_PAD_NANDF_WE_B__GPIO6_12, + /* LCD_PWR_EN */ + MX53_PAD_NANDF_RE_B__GPIO6_13, + /* CSI0_RST */ + MX53_PAD_NANDF_WP_B__GPIO6_9, + /* CSI0_PWN */ + MX53_PAD_NANDF_RB0__GPIO6_10, + /* OSC_CKIH1_EN */ MX53_PAD_NANDF_CS0__GPIO6_11, - - /* AUDMUX3 */ + /* ACCL_INT1_IN */ + MX53_PAD_NANDF_CS2__GPIO6_15, + /* ACCL_INT2_IN */ + MX53_PAD_NANDF_CS3__GPIO6_16, + /* AUDMUX */ MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC, MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD, MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS, MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD, - - /* AUDMUX5 */ - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, - - /* AUD_AMP_STBY_B */ - MX53_PAD_EIM_DA2__GPIO3_2, - - /* DCDC1V8_EN */ - MX53_PAD_EIM_DA1__GPIO3_1, - /* DCDC5V_BB_EN */ - MX53_PAD_KEY_COL4__GPIO4_14, - /*SSI_EXT1_CLK*/ - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, - /* PWM */ - MX53_PAD_GPIO_1__PWM2_PWMO, + /* I2C1 */ + MX53_PAD_CSI0_DAT8__I2C1_SDA, + MX53_PAD_CSI0_DAT9__I2C1_SCL, + /* UART1 */ + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, /* CSI0 */ MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, @@ -228,7 +287,122 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, - /* LDVS */ + /* FEC */ + MX53_PAD_FEC_MDC__FEC_MDC, + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + MX53_PAD_FEC_RXD1__FEC_RDATA_1, + MX53_PAD_FEC_RXD0__FEC_RDATA_0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TDATA_1, + MX53_PAD_FEC_TXD0__FEC_TDATA_0, + /* AUDMUX5 */ + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, + /* MODEM_DISABLE_B */ + MX53_PAD_KEY_COL2__GPIO4_10, + /* SD1_WP */ + MX53_PAD_KEY_ROW2__GPIO4_11, + /* I2C2 */ + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, + /* DCDC5V_BB_EN */ + MX53_PAD_KEY_COL4__GPIO4_14, + /* WLAN_HOST_WAKE */ + MX53_PAD_KEY_ROW4__GPIO4_15, + /* SD1 */ + MX53_PAD_SD1_CMD__ESDHC1_CMD, + MX53_PAD_SD1_CLK__ESDHC1_CLK, + MX53_PAD_SD1_DATA0__ESDHC1_DAT0, + MX53_PAD_SD1_DATA1__ESDHC1_DAT1, + MX53_PAD_SD1_DATA2__ESDHC1_DAT2, + MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD2 */ + MX53_PAD_SD2_CMD__ESDHC2_CMD, + MX53_PAD_SD2_CLK__ESDHC2_CLK, + MX53_PAD_SD2_DATA0__ESDHC2_DAT0, + MX53_PAD_SD2_DATA1__ESDHC2_DAT1, + MX53_PAD_SD2_DATA2__ESDHC2_DAT2, + MX53_PAD_SD2_DATA3__ESDHC2_DAT3, + /* UART2 */ + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + /* DEVELOP_MODE_SW */ + MX53_PAD_PATA_CS_0__GPIO7_9, + /* CABC_EN1 */ + MX53_PAD_PATA_CS_1__GPIO7_10, + /* FEC_nRST */ + MX53_PAD_PATA_DA_0__GPIO7_6, + /* USER_DEBUG_OR_CHARGER_DONE */ + MX53_PAD_PATA_DA_1__GPIO7_7, + /* USB_OTG_PWR_EN */ + MX53_PAD_PATA_DA_2__GPIO7_8, + /* SD3 */ + MX53_PAD_PATA_DATA8__ESDHC3_DAT0, + MX53_PAD_PATA_DATA9__ESDHC3_DAT1, + MX53_PAD_PATA_DATA10__ESDHC3_DAT2, + MX53_PAD_PATA_DATA11__ESDHC3_DAT3, + MX53_PAD_PATA_DATA0__ESDHC3_DAT4, + MX53_PAD_PATA_DATA1__ESDHC3_DAT5, + MX53_PAD_PATA_DATA2__ESDHC3_DAT6, + MX53_PAD_PATA_DATA3__ESDHC3_DAT7, + MX53_PAD_PATA_IORDY__ESDHC3_CLK, + MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + /* FEC_nINT */ + MX53_PAD_PATA_DATA4__GPIO2_4, + /* HEADPHONE DET*/ + MX53_PAD_PATA_DATA5__GPIO2_5, + /* ZigBee_INT*/ + MX53_PAD_PATA_DATA6__GPIO2_6, + /* ZigBee_RESET_B */ + MX53_PAD_PATA_DATA7__GPIO2_7, + /* GPS_RESET_B*/ + MX53_PAD_PATA_DATA12__GPIO2_12, + /* WAKEUP_ZigBee */ + MX53_PAD_PATA_DATA13__GPIO2_13, + /* KEY_VOL- */ + MX53_PAD_PATA_DATA14__GPIO2_14, + /* KEY_VOL+ */ + MX53_PAD_PATA_DATA15__GPIO2_15, + /* DOCK_DECTECT */ + MX53_PAD_PATA_DIOR__GPIO7_3, + /* AC_IN */ + MX53_PAD_PATA_DIOW__GPIO6_17, + /* PWR_GOOD */ + MX53_PAD_PATA_DMACK__GPIO6_18, + /* CABC_EN0 */ + MX53_PAD_PATA_INTRQ__GPIO7_2, + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, + MX53_PAD_GPIO_1__PWM2_PWMO, + /* KEY_RESET */ + MX53_PAD_GPIO_2__GPIO1_2, + /* I2C3 */ + MX53_PAD_GPIO_3__I2C3_SCL, + MX53_PAD_GPIO_6__I2C3_SDA, + /* SATA_CLK_GPEN */ + MX53_PAD_GPIO_4__GPIO1_4, + /* PMIC_FAULT */ + MX53_PAD_GPIO_5__GPIO1_5, + /* SYS_ON_OFF_CTL */ + MX53_PAD_GPIO_7__GPIO1_7, + /* PMIC_ON_OFF_REQ */ + MX53_PAD_GPIO_8__GPIO1_8, + /* CHA_ISET */ + MX53_PAD_GPIO_12__GPIO4_2, + /* SYS_EJECT */ + MX53_PAD_GPIO_13__GPIO4_3, + /* HDMI_CEC_D */ + MX53_PAD_GPIO_14__GPIO4_4, + /* PMIC_INT */ + MX53_PAD_GPIO_16__GPIO7_11, + MX53_PAD_GPIO_17__SPDIF_OUT1, + /* CAP_TCH_FUN1 */ + MX53_PAD_GPIO_18__GPIO7_13, + /* LVDS */ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, @@ -244,7 +418,7 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { }; #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake, debounce_ms) \ { \ .gpio = gpio_num, \ .type = EV_KEY, \ @@ -252,12 +426,13 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { .active_low = act_low, \ .desc = "btn " descr, \ .wakeup = wake, \ + .debounce_interval = debounce_ms, \ } static struct gpio_keys_button smd_buttons[] = { - GPIO_BUTTON(MX53_SMD_NONKEY, KEY_POWER, 1, "power", 0), - GPIO_BUTTON(MX53_SMD_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(MX53_SMD_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), + GPIO_BUTTON(MX53_SMD_PMIC_ON_OFF_REQ, KEY_POWER, 0, "power", 0, 100), + GPIO_BUTTON(MX53_SMD_UI1, KEY_VOLUMEUP, 1, "volume-up", 0, 0), + GPIO_BUTTON(MX53_SMD_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0, 0), }; static struct gpio_keys_platform_data smd_button_data = { @@ -284,6 +459,8 @@ static void __init smd_add_device_buttons(void) {} static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { .flags = IMXUART_HAVE_RTSCTS, + .dma_req_rx = MX53_DMA_REQ_UART3_RX, + .dma_req_tx = MX53_DMA_REQ_UART3_TX, }; static inline void mx53_smd_init_uart(void) @@ -304,6 +481,7 @@ static inline void mx53_smd_fec_reset(void) return; } gpio_direction_output(SMD_FEC_PHY_RST, 0); + gpio_set_value(SMD_FEC_PHY_RST, 0); msleep(1); gpio_set_value(SMD_FEC_PHY_RST, 1); } @@ -316,17 +494,38 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { .bitrate = 100000, }; +extern void __iomem *tzic_base; +static void smd_da9053_irq_wakeup_only_fixup(void) +{ + if (NULL == tzic_base) { + pr_err("fail to map MX53_TZIC_BASE_ADDR\n"); + return; + } + __raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET); + __raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET); + __raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET); + /* only enable irq wakeup for da9053 */ + __raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET); + pr_info("only da9053 irq is wakeup-enabled\n"); +} + static void smd_suspend_enter(void) { - /* da9053 suspend preparation */ + if (board_is_rev(IMX_BOARD_REV_4)) { + smd_da9053_irq_wakeup_only_fixup(); + da9053_suspend_cmd_sw(); + } else { + if (da9053_get_chip_version() != DA9053_VERSION_BB) + smd_da9053_irq_wakeup_only_fixup(); + + da9053_suspend_cmd_hw(); + } } static void smd_suspend_exit(void) { - /*clear the EMPGC0/1 bits */ - __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); - /* da9053 resmue resore */ + if (da9053_get_chip_version()) + da9053_restore_volt_settings(); } static struct mxc_pm_platform_data smd_pm_data = { @@ -334,18 +533,22 @@ static struct mxc_pm_platform_data smd_pm_data = { .suspend_exit = smd_suspend_exit, }; - +/* SDIO Card Slot */ static const struct esdhc_platform_data mx53_smd_sd1_data __initconst = { .cd_gpio = MX53_SMD_SD1_CD, .wp_gpio = MX53_SMD_SD1_WP, }; +/* SDIO Wifi */ static const struct esdhc_platform_data mx53_smd_sd2_data __initconst = { .always_present = 1, + .keep_power_at_suspend = 1, }; +/* SDIO Internal eMMC */ static const struct esdhc_platform_data mx53_smd_sd3_data __initconst = { .always_present = 1, + .support_8bit = 1, }; static struct fsl_mxc_camera_platform_data camera_data = { @@ -359,13 +562,16 @@ static struct fsl_mxc_lightsensor_platform_data ls_data = { .rext = 700, /* calibration: 499K->700K */ }; +static int mma8451_position = 4; + static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { { .type = "mma8451", .addr = 0x1C, + .platform_data = (void *)&mma8451_position, }, { - .type = "ov3640", + .type = "ov5642", .addr = 0x3C, .platform_data = (void *)&camera_data, }, @@ -382,10 +588,12 @@ static struct mpr121_platform_data mpr121_keyboard_platdata = { .matrix = smd_touchkey_martix, }; +static int mag3110_position = 6; + static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { { - .type = "sgtl5000", - .addr = 0x0a, + .type = "sgtl5000", + .addr = 0x0a, }, { .type = "mpr121_touchkey", @@ -393,6 +601,12 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { .irq = gpio_to_irq(MX53_SMD_KEY_INT), .platform_data = &mpr121_keyboard_platdata, }, + { + .type = "mag3110", + .addr = 0x0e, + .irq = gpio_to_irq(MX53_SMD_eCOMPASS_INT), + .platform_data = (void *)&mag3110_position, + }, }; static int mx53_smd_spi_cs[] = { @@ -405,6 +619,7 @@ static struct spi_imx_master mx53_smd_spi_data = { .num_chipselect = ARRAY_SIZE(mx53_smd_spi_cs), }; + #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) static struct mtd_partition m25p32_partitions[] = { { @@ -490,6 +705,27 @@ static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = { .analog_reg = "DA9052_LDO2", }; +static struct android_pmem_platform_data android_pmem_data = { + .name = "pmem_adsp", + .size = SZ_64M, + .cached = 0, +}; + +static struct android_pmem_platform_data android_pmem_gpu_data = { + .name = "pmem_gpu", + .size = SZ_64M, + .cached = 1, +}; + +static int p1003_ts_hw_status(void) +{ + return gpio_get_value(MX53_SMD_CAP_TCH_INT1); +} + +static struct p1003_ts_platform_data p1003_ts_data = { + .hw_status = p1003_ts_hw_status, +}; + static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { { .type = "sii902x", @@ -498,8 +734,15 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { .platform_data = &sii902x_hdmi_data, }, { - I2C_BOARD_INFO("p1003_ts", 0x41), - .irq = gpio_to_irq(MX53_SMD_CAP_TCH_INT1), + .type = "p1003_fwv33", + .addr = 0x41, + .irq = gpio_to_irq(MX53_SMD_CAP_TCH_INT1), + .platform_data = &p1003_ts_data, + }, + { + .type = "egalax_ts", + .addr = 0x4, + .irq = gpio_to_irq(MX53_SMD_CAP_TCH_INT1), }, { .type = "isl29023", @@ -507,7 +750,6 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { .irq = gpio_to_irq(MX53_SMD_ALS_INT), .platform_data = &ls_data, }, - }; /* HW Initialization, if return 0, initialization is successful. */ @@ -662,6 +904,18 @@ static int smd_sgtl5000_init(void) /* Enable OSC_CKIH1_EN for audio */ gpio_request(MX53_SMD_OSC_CKIH1_EN, "osc-en"); gpio_direction_output(MX53_SMD_OSC_CKIH1_EN, 1); + gpio_set_value(MX53_SMD_OSC_CKIH1_EN, 1); + return 0; +} + +static int smd_sgtl5000_amp_enable(int enable) +{ + gpio_request(MX53_SMD_AUD_AMP_STBY_B, "amp-standby"); + if (enable) + gpio_direction_output(MX53_SMD_AUD_AMP_STBY_B, 1); + else + gpio_direction_output(MX53_SMD_AUD_AMP_STBY_B, 0); + gpio_free(MX53_SMD_AUD_AMP_STBY_B); return 0; } @@ -670,6 +924,7 @@ static struct mxc_audio_platform_data smd_audio_data = { .src_port = 2, .ext_port = 5, .init = smd_sgtl5000_init, + .amp_enable = smd_sgtl5000_amp_enable, .hp_gpio = MX53_SMD_HEADPHONE_DEC, .hp_active_low = 1, }; @@ -688,18 +943,25 @@ static struct fsl_mxc_lcd_platform_data lcdif_data = { .default_ifmt = IPU_PIX_FMT_RGB565, }; +static struct imx_asrc_platform_data imx_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2, +}; + static struct ipuv3_fb_platform_data smd_fb_data[] = { { .disp_dev = "ldb", .interface_pix_fmt = IPU_PIX_FMT_RGB666, .mode_str = "LDB-XGA", - .default_bpp = 16, + .default_bpp = 32, .int_clk = false, + .panel_width_mm = 203, + .panel_height_mm = 152, }, { - .disp_dev = "hdmi", + .disp_dev = "sii902x_hdmi", .interface_pix_fmt = IPU_PIX_FMT_RGB24, - .mode_str = "1024x768M-16@60", - .default_bpp = 16, + .mode_str = "1024x768M-32@60", + .default_bpp = 32, .int_clk = false, }, }; @@ -713,7 +975,11 @@ static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { .pwm_id = 1, .max_brightness = 255, .dft_brightness = 128, - .pwm_period_ns = 50000, + .pwm_period_ns = 45454, +}; + +static struct mxc_gpu_platform_data mx53_smd_gpu_pdata __initdata = { + .enable_mmu = 0, }; static struct fsl_mxc_ldb_platform_data ldb_data = { @@ -738,14 +1004,153 @@ static struct mxc_spdif_platform_data mxc_spdif_data = { .spdif_clk = NULL, /* spdif bus clk */ }; +static struct mxc_dvfs_platform_data smd_dvfs_core_data = { + .reg_id = "cpu_vddgp", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + static struct mxc_regulator_platform_data smd_regulator_data = { - .cpu_reg_id = "DA9052_BUCK_CORE", + .cpu_reg_id = "cpu_vddgp", }; +#if defined(CONFIG_BATTERY_MAX17085) || defined(CONFIG_BATTERY_MAX17085_MODULE) +static struct resource smd_batt_resource[] = { + { + .flags = IORESOURCE_IO, + .name = "pwr-good", + .start = MX53_SMD_PWR_GOOD, + .end = MX53_SMD_PWR_GOOD, + }, + { + .flags = IORESOURCE_IO, + .name = "ac-in", + .start = MX53_SMD_AC_IN, + .end = MX53_SMD_AC_IN, + }, + { + .flags = IORESOURCE_IO, + .name = "charge-now", + .start = MX53_SMD_CHRG_OR_CMOS, + .end = MX53_SMD_CHRG_OR_CMOS, + }, + { + .flags = IORESOURCE_IO, + .name = "charge-done", + .start = MX53_SMD_USER_DEG_CHG_NONE, + .end = MX53_SMD_USER_DEG_CHG_NONE, + }, +}; + +static struct platform_device smd_battery_device = { + .name = "max17085_bat", + .resource = smd_batt_resource, + .num_resources = ARRAY_SIZE(smd_batt_resource), +}; + +static void __init smd_add_device_battery(void) +{ + platform_device_register(&smd_battery_device); +} +#else +static void __init smd_add_device_battery(void) +{ +} +#endif + +extern struct imx_mxc_gpu_data imx53_gpu_data; + static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { + char *str; + struct tag *t; + int i = 0; + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { + str = t->u.cmdline.cmdline; + str = strstr(str, "pmem="); + if (str != NULL) { + str += 5; + android_pmem_gpu_data.size = + memparse(str, &str); + if (*str == ',') { + str++; + android_pmem_data.size = + memparse(str, &str); + } + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "fbmem="); + if (str != NULL) { + str += 6; + smd_fb_data[i++].res_size[0] = + memparse(str, &str); + while (*str == ',' && + i < ARRAY_SIZE(smd_fb_data)) { + str++; + smd_fb_data[i++].res_size[0] = + memparse(str, &str); + } + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + imx53_gpu_data.gmem_reserved_size = + memparse(str, &str); + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "fs_sdcard="); + if (str != NULL) { + str += 10; + fs_in_sdcard = memparse(str, &str); + } + break; + } + } +} + +static void mx53_smd_power_off(void) +{ + /* power off by sending shutdown command to da9053*/ + da9053_power_off(); +} + +static int __init mx53_smd_power_init(void) +{ + /* cpu get regulator needs to be in lateinit so that + regulator list gets updated for i2c da9052 regulators */ + mx5_cpu_regulator_init(); + + if (machine_is_mx53_smd()) + pm_power_off = mx53_smd_power_off; + + return 0; } +late_initcall(mx53_smd_power_init); static void __init mx53_smd_board_init(void) { @@ -754,12 +1159,70 @@ static void __init mx53_smd_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, ARRAY_SIZE(mx53_smd_pads)); + /* Enable MX53_SMD_DCDC1V8_EN */ + gpio_request(MX53_SMD_DCDC1V8_EN, "dcdc1v8-en"); + gpio_direction_output(MX53_SMD_DCDC1V8_EN, 1); + gpio_set_value(MX53_SMD_DCDC1V8_EN, 1); + + /* Sii902x HDMI controller */ + gpio_request(MX53_SMD_HDMI_RESET_B, "disp0-pwr-en"); + gpio_direction_output(MX53_SMD_HDMI_RESET_B, 0); + gpio_request(MX53_SMD_HDMI_INT, "disp0-det-int"); + gpio_direction_input(MX53_SMD_HDMI_INT); + + /* MPR121 capacitive button */ + gpio_request(MX53_SMD_KEY_INT, "cap-button-irq"); + gpio_direction_input(MX53_SMD_KEY_INT); + gpio_free(MX53_SMD_KEY_INT); + + /* Camera reset */ + gpio_request(MX53_SMD_CSI0_RST, "cam-reset"); + gpio_set_value(MX53_SMD_CSI0_RST, 1); + + /* Camera power down */ + gpio_request(MX53_SMD_CSI0_PWN, "cam-pwdn"); + gpio_direction_output(MX53_SMD_CSI0_PWN, 1); + msleep(1); + gpio_set_value(MX53_SMD_CSI0_PWN, 0); + + /* Enable WiFi/BT Power*/ + gpio_request(MX53_SMD_WiFi_BT_PWR_EN, "bt-wifi-pwren"); + gpio_direction_output(MX53_SMD_WiFi_BT_PWR_EN, 1); + gpio_free(MX53_SMD_WiFi_BT_PWR_EN); + + /* WiFi Power up sequence */ + gpio_request(MX53_SMD_WLAN_PD, "wifi-pd"); + gpio_direction_output(MX53_SMD_WLAN_PD, 1); + mdelay(1); + gpio_set_value(MX53_SMD_WLAN_PD, 0); + mdelay(5); + gpio_set_value(MX53_SMD_WLAN_PD, 1); + gpio_free(MX53_SMD_WLAN_PD); + + /* battery */ + gpio_request(MX53_SMD_AC_IN, "ac-in"); + gpio_direction_input(MX53_SMD_AC_IN); + gpio_request(MX53_SMD_PWR_GOOD, "pwr-good"); + gpio_direction_input(MX53_SMD_PWR_GOOD); + gpio_request(MX53_SMD_CHRG_OR_CMOS, "charger now"); + gpio_direction_output(MX53_SMD_CHRG_OR_CMOS, 0); + gpio_request(MX53_SMD_USER_DEG_CHG_NONE, "charger done"); + gpio_direction_output(MX53_SMD_USER_DEG_CHG_NONE, 0); + + /* ambient light sensor */ + gpio_request(MX53_SMD_ALS_INT, "als int"); + gpio_direction_input(MX53_SMD_ALS_INT); + + gpio_request(MX53_SMD_LCD_PWR_EN, "lcd-pwr-en"); + gpio_direction_output(MX53_SMD_LCD_PWR_EN, 1); + + /* mag3110 magnetometer sensor */ + gpio_request(MX53_SMD_eCOMPASS_INT, "ecompass int"); + gpio_direction_input(MX53_SMD_eCOMPASS_INT); + gp_reg_id = smd_regulator_data.cpu_reg_id; lp_reg_id = smd_regulator_data.vcc_reg_id; - mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); - clk_put(mxc_spdif_data.spdif_core_clk); - mx53_smd_init_uart(); mx53_smd_fec_reset(); mxc_register_device(&mxc_pm_device, &smd_pm_data); @@ -775,34 +1238,36 @@ static void __init mx53_smd_board_init(void) for (i = 0; i < ARRAY_SIZE(smd_fb_data); i++) imx53_add_ipuv3fb(i, &smd_fb_data[i]); imx53_add_lcdif(&lcdif_data); - imx53_add_vpu(); + if (!mxc_fuse_get_vpu_status()) + imx53_add_vpu(); imx53_add_ldb(&ldb_data); imx53_add_v4l2_output(0); imx53_add_v4l2_capture(0); imx53_add_mxc_pwm(1); imx53_add_mxc_pwm_backlight(0, &mxc_pwm_backlight_data); - imx53_add_sdhci_esdhc_imx(0, &mx53_smd_sd1_data); - imx53_add_sdhci_esdhc_imx(1, &mx53_smd_sd2_data); - imx53_add_sdhci_esdhc_imx(2, &mx53_smd_sd3_data); + + if (fs_in_sdcard == 1) { + imx53_add_sdhci_esdhc_imx(0, &mx53_smd_sd1_data); + imx53_add_sdhci_esdhc_imx(1, &mx53_smd_sd2_data); + imx53_add_sdhci_esdhc_imx(2, &mx53_smd_sd3_data); + } else { + imx53_add_sdhci_esdhc_imx(2, &mx53_smd_sd3_data); + imx53_add_sdhci_esdhc_imx(1, &mx53_smd_sd2_data); + imx53_add_sdhci_esdhc_imx(0, &mx53_smd_sd1_data); + } + imx53_add_ahci(0, &mx53_smd_sata_data); mxc_register_device(&imx_ahci_device_hwmon, NULL); - mx53_smd_init_usb(); + imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + imx53_add_asrc(&imx_asrc_data); + imx53_add_iim(&iim_data); smd_add_device_buttons(); mx53_smd_init_da9052(); - /* Camera reset */ - gpio_request(MX53_SMD_CSI0_RST, "cam-reset"); - gpio_set_value(MX53_SMD_CSI0_RST, 1); - - /* Camera power down */ - gpio_request(MX53_SMD_CSI0_PWN, "cam-pwdn"); - gpio_direction_output(MX53_SMD_CSI0_PWN, 1); - msleep(1); - gpio_set_value(MX53_SMD_CSI0_PWN, 0); - spi_device_init(); i2c_register_board_info(0, mxc_i2c0_board_info, @@ -812,44 +1277,114 @@ static void __init mx53_smd_board_init(void) i2c_register_board_info(2, mxc_i2c2_board_info, ARRAY_SIZE(mxc_i2c2_board_info)); + mxc_register_device(&imx_bt_rfkill, &imx_bt_rfkill_data); - gpio_request(MX53_SMD_DCDC1V8_EN, "dcdc1v8-en"); - gpio_direction_output(MX53_SMD_DCDC1V8_EN, 1); - - /* ambient light sensor */ - gpio_request(MX53_SMD_ALS_INT, "als int"); - gpio_direction_input(MX53_SMD_ALS_INT); + imx53_add_imx_ssi(1, &smd_ssi_pdata); mxc_register_device(&smd_audio_device, &smd_audio_data); - mxc_register_device(&imx_bt_rfkill, &imx_bt_rfkill_data); - imx53_add_imx_ssi(1, &smd_ssi_pdata); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); imx53_add_spdif(&mxc_spdif_data); imx53_add_spdif_dai(); imx53_add_spdif_audio_device(); + mxc_register_device(&mxc_android_pmem_device, &android_pmem_data); + mxc_register_device(&mxc_android_pmem_gpu_device, + &android_pmem_gpu_data); + + /*GPU*/ + if (mx53_revision() >= IMX_CHIP_REVISION_2_0) + mx53_smd_gpu_pdata.z160_revision = 1; + else + mx53_smd_gpu_pdata.z160_revision = 0; + + if (!mxc_fuse_get_gpu_status()) + imx53_add_mxc_gpu(&mx53_smd_gpu_pdata); + /* this call required to release SCC RAM partition held by ROM * during boot, even if SCC2 driver is not part of the image */ imx53_add_mxc_scc2(); + smd_add_device_battery(); + pm_i2c_init(MX53_I2C1_BASE_ADDR); - mx5_cpu_regulator_init(); + imx53_add_dvfs_core(&smd_dvfs_core_data); + imx53_add_busfreq(); } static void __init mx53_smd_timer_init(void) { + struct clk *uart_clk; + mx53_clocks_init(32768, 24000000, 22579200, 0); + + uart_clk = clk_get_sys("imx-uart.0", NULL); + early_console_setup(MX53_UART1_BASE_ADDR, uart_clk); } static struct sys_timer mx53_smd_timer = { .init = mx53_smd_timer_init, }; -MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") +#define SZ_TRIPLE_1080P ALIGN((1920*ALIGN(1080, 128)*2*3), SZ_4K) +static void __init mx53_smd_reserve(void) +{ + phys_addr_t phys; + int i; + + if (imx53_gpu_data.gmem_reserved_size) { + phys = memblock_alloc(imx53_gpu_data.gmem_reserved_size, + SZ_4K); + memblock_free(phys, imx53_gpu_data.gmem_reserved_size); + memblock_remove(phys, imx53_gpu_data.gmem_reserved_size); + imx53_gpu_data.gmem_reserved_base = phys; + } +#ifdef CONFIG_ANDROID_PMEM + if (android_pmem_data.size) { + phys = memblock_alloc(android_pmem_data.size, SZ_4K); + memblock_free(phys, android_pmem_data.size); + memblock_remove(phys, android_pmem_data.size); + android_pmem_data.start = phys; + } + + if (android_pmem_gpu_data.size) { + phys = memblock_alloc(android_pmem_gpu_data.size, SZ_4K); + memblock_free(phys, android_pmem_gpu_data.size); + memblock_remove(phys, android_pmem_gpu_data.size); + android_pmem_gpu_data.start = phys; + } +#endif + + for (i = 0; i < ARRAY_SIZE(smd_fb_data); i++) + if (smd_fb_data[i].res_size[0]) { + /* reserve for background buffer */ + phys = memblock_alloc(smd_fb_data[i].res_size[0], + SZ_4K); + memblock_free(phys, smd_fb_data[i].res_size[0]); + memblock_remove(phys, smd_fb_data[i].res_size[0]); + smd_fb_data[i].res_base[0] = phys; + + /* reserve for overlay buffer */ + phys = memblock_alloc(SZ_TRIPLE_1080P, SZ_4K); + memblock_free(phys, SZ_TRIPLE_1080P); + memblock_remove(phys, SZ_TRIPLE_1080P); + smd_fb_data[i].res_base[1] = phys; + smd_fb_data[i].res_size[1] = SZ_TRIPLE_1080P; + } +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX53_SMD data structure. + */ +MACHINE_START(MX53_SMD, "Freescale iMX53 SMD Board") + /* Maintainer: Freescale Semiconductor, Inc. */ .fixup = fixup_mxc_board, .map_io = mx53_map_io, .init_early = imx53_init_early, .init_irq = mx53_init_irq, .timer = &mx53_smd_timer, .init_machine = mx53_smd_board_init, + .reserve = mx53_smd_reserve, MACHINE_END diff --git a/arch/arm/mach-mx5/check_fuse.c b/arch/arm/mach-mx5/check_fuse.c new file mode 100644 index 000000000000..a4ae656e7462 --- /dev/null +++ b/arch/arm/mach-mx5/check_fuse.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <mach/hardware.h> +#include <mach/check_fuse.h> + +int mxc_fuse_get_gpu_status(void) +{ + void __iomem *reg_base = NULL; + u32 reg_val = 0; + int bit_status = 0; + + if (cpu_is_mx53() || cpu_is_mx51()) { + reg_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); + reg_val = readl(reg_base + MXC_IIM_MX5_DISABLERS_OFFSET); + bit_status = (reg_val & MXC_IIM_MX5_DISABLERS_GPU_MASK) + >> MXC_IIM_MX5_DISABLERS_GPU_SHIFT; + } else if (cpu_is_mx50()) { + reg_base = ioremap(MX50_OCOTP_CTRL_BASE_ADDR, SZ_8K); + reg_val = readl(reg_base + FSL_OCOTP_MX5_CFG2_OFFSET); + bit_status = (reg_val & FSL_OCOTP_MX5_DISABLERS_GPU_MASK) + >> FSL_OCOTP_MX5_DISABLERS_GPU_SHIFT; + } + + return (1 == bit_status); +} +EXPORT_SYMBOL(mxc_fuse_get_gpu_status); + +int mxc_fuse_get_vpu_status(void) +{ + void __iomem *reg_base = NULL; + u32 reg_val = 0; + int bit_status = 0; + + if (cpu_is_mx53()) { + reg_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); + reg_val = readl(reg_base + MXC_IIM_MX5_DISABLERS_OFFSET); + bit_status = (reg_val & MXC_IIM_MX5_DISABLERS_VPU_MASK) + >> MXC_IIM_MX5_DISABLERS_VPU_SHIFT; + } + + return (1 == bit_status); +} +EXPORT_SYMBOL(mxc_fuse_get_vpu_status); + diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index bf60ffa6ef8f..e1f26f88961b 100755 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -54,7 +54,7 @@ static struct clk axi_a_clk; static struct clk axi_b_clk; static struct clk ddr_hf_clk; static struct clk mipi_hsp_clk; -static struct clk gpu3d_clk; +static struct clk gpu3d_clk[]; static struct clk gpu2d_clk; static struct clk vpu_clk[]; static int cpu_curr_op; @@ -103,7 +103,6 @@ extern int dvfs_core_is_active; extern int mxc_jtag_enabled; extern int uart_at_24; -extern int cpufreq_trig_needed; extern int low_bus_freq_mode; static int cpu_clk_set_op(int op); @@ -148,6 +147,11 @@ static int _clk_enable(struct clk *clk) reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift; __raw_writel(reg, clk->enable_reg); + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + return 0; } @@ -168,6 +172,11 @@ static void _clk_disable(struct clk *clk) reg = __raw_readl(clk->enable_reg); reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; } static void _clk_disable_inwait(struct clk *clk) @@ -310,17 +319,6 @@ static struct clk fpm_clk = { .disable = _fpm_disable, }; -static unsigned long _fpm_div2_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 2; -} - -static struct clk fpm_div2_clk = { - __INIT_CLK_DEBUG(fpm_div2_clk) - .parent = &fpm_clk, - .get_rate = _fpm_div2_get_rate, -}; - static unsigned long _clk_pll_get_rate(struct clk *clk) { long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; @@ -380,6 +378,9 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) unsigned long quad_parent_rate; unsigned long pll_hfsm, dp_ctl; + if(clk_get_rate(clk) == rate) + return 0; + pllbase = _get_pll_base(clk); quad_parent_rate = 4 * clk_get_rate(clk->parent); @@ -621,6 +622,9 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) { u32 i; + if(clk_get_rate(clk) == rate) + return 0; + for (i = 0; i < cpu_op_nr; i++) { if (rate == cpu_op_tbl[i].cpu_rate) break; @@ -693,7 +697,8 @@ static unsigned long _clk_main_bus_get_rate(struct clk *clk) { u32 div = 0; - if (dvfs_per_divider_active() || low_bus_freq_mode) + if (cpu_is_mx51() && + (dvfs_per_divider_active() || low_bus_freq_mode)) div = (__raw_readl(MXC_CCM_CDCR) & 0x3); return clk_get_rate(clk->parent) / (div + 1); } @@ -747,6 +752,9 @@ static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -846,6 +854,9 @@ static int _clk_ddr_hf_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -900,6 +911,9 @@ static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -978,6 +992,9 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -1125,6 +1142,9 @@ static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -1358,14 +1378,21 @@ static struct clk ocram_clk = { }; -static struct clk aips_tz1_clk = { - __INIT_CLK_DEBUG(aips_tz1_clk) +static struct clk aips_tz1_clk[] = { + { + __INIT_CLK_DEBUG(aips_tz1_clk_0) .parent = &ahb_clk, - .secondary = &ahb_max_clk, + .secondary = &aips_tz1_clk[1], .enable_reg = MXC_CCM_CCGR0, .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, .enable = _clk_enable, .disable = _clk_disable_inwait, + }, + { + __INIT_CLK_DEBUG(aips_tz1_clk_1) + .parent = &emi_fast_clk, + .secondary = &ahb_max_clk, + }, }; static struct clk aips_tz2_clk = { @@ -1420,7 +1447,7 @@ static void _clk_sdma_disable(struct clk *clk) static struct clk sdma_clk[] = { { - __INIT_CLK_DEBUG(sdma_clk) + __INIT_CLK_DEBUG(sdma_clk_0) .parent = &ahb_clk, .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, @@ -1428,11 +1455,14 @@ static struct clk sdma_clk[] = { .disable = _clk_sdma_disable, }, { - .parent = &ipg_clk, + __INIT_CLK_DEBUG(sdma_clk_1) + .parent = &ipg_clk, #ifdef CONFIG_SDMA_IRAM - .secondary = &emi_intr_clk[0], + .secondary = &emi_intr_clk[0], +#else + .secondary = &emi_fast_clk, #endif - }, + }, }; static int _clk_ipu_enable(struct clk *clk) @@ -1571,6 +1601,9 @@ static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate) u32 reg, div; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -1701,6 +1734,9 @@ static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate) u32 reg, div = 0; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + if (rate * 7 <= parent_rate + parent_rate/20) { div = 7; rate = parent_rate / 7; @@ -1812,6 +1848,9 @@ static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -1887,6 +1926,9 @@ static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -2052,6 +2094,9 @@ static int _clk_tve_set_rate(struct clk *clk, unsigned long rate) if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) return -EINVAL; + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -2140,7 +2185,7 @@ static struct clk uart1_clk[] = { .id = 0, .parent = &ipg_clk, #if UART1_DMA_ENABLE - .secondary = &aips_tz1_clk, + .secondary = &aips_tz1_clk[0], #endif .enable_reg = MXC_CCM_CCGR1, .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, @@ -2168,7 +2213,7 @@ static struct clk uart2_clk[] = { .id = 1, .parent = &ipg_clk, #if UART2_DMA_ENABLE - .secondary = &aips_tz1_clk, + .secondary = &aips_tz1_clk[0], #endif .enable_reg = MXC_CCM_CCGR1, .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, @@ -2391,17 +2436,6 @@ static struct clk hsi2c_serial_clk = { .disable = _clk_disable, }; -static struct clk hsi2c_clk = { - __INIT_CLK_DEBUG(hsi2c_clk) - .id = 0, - .parent = &ipg_clk, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, -}; - static unsigned long _clk_cspi_get_rate(struct clk *clk) { u32 reg, prediv, podf; @@ -2417,6 +2451,32 @@ static unsigned long _clk_cspi_get_rate(struct clk *clk) return clk_get_rate(clk->parent) / (prediv * podf); } +static int _clk_cspi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + if(clk_get_rate(clk) == rate) + return 0; + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate)) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CSCDR2) & + ~(MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK | + MXC_CCM_CSCDR2_ECSPI_CLK_PRED_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR2_ECSPI_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; @@ -2434,6 +2494,7 @@ static struct clk cspi_main_clk = { __INIT_CLK_DEBUG(cspi_main_clk) .parent = &pll3_sw_clk, .get_rate = _clk_cspi_get_rate, + .set_rate = _clk_cspi_set_rate, .set_parent = _clk_cspi_set_parent, }; @@ -2761,7 +2822,7 @@ static struct clk ssi3_clk[] = { .id = 2, .parent = &aips_tz2_clk, #ifdef CONFIG_SND_MXC_SOC_IRAM - .secondary = &emi_intr_clk, + .secondary = &emi_intr_clk[0], #else .secondary = &emi_fast_clk, #endif @@ -2790,6 +2851,9 @@ static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate) u32 reg, div, pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -2962,25 +3026,26 @@ static unsigned long _clk_esai_get_rate(struct clk *clk) static struct clk esai_clk[] = { { __INIT_CLK_DEBUG(esai_clk_0) - .id = 0, - .parent = &pll3_sw_clk, - .set_parent = _clk_esai_set_parent, - .get_rate = _clk_esai_get_rate, - .secondary = &esai_clk[1], - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - }, + .id = 0, + .parent = &pll3_sw_clk, + .secondary = &spba_clk, + .set_parent = _clk_esai_set_parent, + .get_rate = _clk_esai_get_rate, + .secondary = &esai_clk[1], + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, { __INIT_CLK_DEBUG(esai_clk_1) - .id = 0, - .parent = &ipg_clk, - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - }, + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, }; static struct clk iim_clk = { @@ -2995,35 +3060,35 @@ static struct clk iim_clk = { static struct clk tmax1_clk = { __INIT_CLK_DEBUG(tmax1_clk) - .id = 0, - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, - .disable = _clk_disable, - }; + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, +}; static struct clk tmax2_clk = { __INIT_CLK_DEBUG(tmax2_clk) - .id = 0, - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, - .disable = _clk_disable, + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, }; static struct clk tmax3_clk = { __INIT_CLK_DEBUG(tmax3_clk) - .id = 0, - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, - .disable = _clk_disable, + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, }; static unsigned long _clk_usboh3_get_rate(struct clk *clk) @@ -3190,6 +3255,9 @@ static int _clk_sdhc1_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -3287,6 +3355,9 @@ static int _clk_esdhc2_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + if (cpu_is_mx51()) { div = parent_rate / rate; @@ -3383,6 +3454,9 @@ static int _clk_sdhc3_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + if (cpu_is_mx53()) { div = parent_rate / rate; @@ -3496,6 +3570,7 @@ static struct clk sata_clk = { .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, .disable = _clk_disable, + .secondary = &emi_fast_clk, }; static struct clk ieee_1588_clk = { @@ -3626,6 +3701,9 @@ static int _clk_sim_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -3715,6 +3793,9 @@ static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -3819,6 +3900,7 @@ static struct clk spdif0_clk[] = { __INIT_CLK_DEBUG(spdif0_clk_0) .id = 0, .parent = &pll3_sw_clk, + .secondary = &spba_clk, .set_parent = _clk_spdif0_set_parent, .get_rate = _clk_spdif0_get_rate, .enable = _clk_enable, @@ -3878,6 +3960,7 @@ static struct clk spdif1_clk[] = { __INIT_CLK_DEBUG(spdif1_clk_0) .id = 1, .parent = &pll3_sw_clk, + .secondary = &spba_clk, .set_parent = _clk_spdif1_set_parent, .get_rate = _clk_spdif1_get_rate, .enable = _clk_enable, @@ -3999,6 +4082,7 @@ static struct clk vpu_clk[] = { { __INIT_CLK_DEBUG(vpu_clk_2) .parent = &emi_fast_clk, + .secondary = &emi_intr_clk[0], } }; @@ -4020,23 +4104,6 @@ static struct clk lpsr_clk = { .set_parent = _clk_lpsr_set_parent, }; -static unsigned long _clk_pgc_get_rate(struct clk *clk) -{ - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CSCDR1); - div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET; - div = 1 >> div; - return clk_get_rate(clk->parent) / div; -} - -static struct clk pgc_clk = { - __INIT_CLK_DEBUG(pgc_clk) - .parent = &ipg_clk, - .get_rate = _clk_pgc_get_rate, -}; - static unsigned long _clk_usb_get_rate(struct clk *clk) { return 60000000; @@ -4066,15 +4133,21 @@ static struct clk rtc_clk = { .disable = _clk_disable, }; -static struct clk ata_clk = { - __INIT_CLK_DEBUG(ata_clk) - .parent = &ipg_clk, - .secondary = &spba_clk, +static struct clk ata_clk[] = { + { + __INIT_CLK_DEBUG(ata_clk_0) + .parent = &spba_clk, + .secondary = &ata_clk[1], .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, .disable = _clk_disable, .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + __INIT_CLK_DEBUG(ata_clk_1) + .parent = &emi_fast_clk, + } }; static struct clk owire_clk = { @@ -4147,7 +4220,7 @@ static struct clk sahara_clk[] = { .secondary = &sahara_clk[2], }, { - .parent = &scc_clk, + .parent = &scc_clk[0], .secondary = &emi_fast_clk, } }; @@ -4176,8 +4249,9 @@ static struct clk garb_clk = { .disable = _clk_disable, }; -static struct clk gpu3d_clk = { - __INIT_CLK_DEBUG(gpu3d_clk) +static struct clk gpu3d_clk[] = { + { + __INIT_CLK_DEBUG(gpu3d_clk_0) .parent = &axi_a_clk, .set_parent = _clk_gpu3d_set_parent, .enable = _clk_enable, @@ -4185,7 +4259,13 @@ static struct clk gpu3d_clk = { .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, .disable = _clk_disable, .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .secondary = &gpu3d_clk[1], + }, + { + __INIT_CLK_DEBUG(gpu3d_clk_1) + .parent = &emi_fast_clk, .secondary = &garb_clk, + } }; static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) @@ -4205,6 +4285,7 @@ static struct clk gpu2d_clk = { __INIT_CLK_DEBUG(gpu2d_clk) .parent = &axi_a_clk, .set_parent = _clk_gpu2d_set_parent, + .secondary = &emi_fast_clk, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR6, .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, @@ -4246,6 +4327,9 @@ static int cko1_set_rate(struct clk *clk, unsigned long rate) u32 reg, div; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = (parent_rate/rate - 1) & 0x7; reg = __raw_readl(MXC_CCM_CCOSR); reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK; @@ -4347,6 +4431,9 @@ static int _clk_asrc_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if(clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -4384,6 +4471,7 @@ static struct clk asrc_clk[] = { __INIT_CLK_DEBUG(asrc_clk_0) .id = 0, .parent = &pll4_sw_clk, + .secondary = &spba_clk, .set_parent = _clk_asrc_set_parent, .get_rate = _clk_asrc_get_rate, .set_rate = _clk_asrc_set_rate, @@ -4404,6 +4492,10 @@ static struct clk asrc_clk[] = { }, }; +static struct clk dummy_clk = { + .id = 0, +}; + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -4433,6 +4525,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "vpu_core_clk", vpu_clk[1]), _REGISTER_CLOCK(NULL, "nfc_clk", emi_enfc_clk), _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]), + _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[1]), _REGISTER_CLOCK(NULL, "ipu1_clk", ipu_clk[0]), _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu_di_clk[0]), _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu_di_clk[1]), @@ -4473,10 +4566,10 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_vpu.0", NULL, vpu_clk[0]), _REGISTER_CLOCK(NULL, "lpsr_clk", lpsr_clk), _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk), - _REGISTER_CLOCK("pata_fsl", NULL, ata_clk), + _REGISTER_CLOCK("pata_fsl", NULL, ata_clk[0]), _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), _REGISTER_CLOCK(NULL, "sahara_clk", sahara_clk[0]), - _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk), + _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk[0]), _REGISTER_CLOCK(NULL, "garb_clk", garb_clk), _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_clk), _REGISTER_CLOCK("mxc_scc.0", NULL, scc_clk[0]), @@ -4484,6 +4577,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]), _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]), _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), + _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk), + _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk), }; static struct clk_lookup mx51_lookups[] = { @@ -4584,7 +4679,6 @@ static void clk_tree_init(void) int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { - __iomem void *base; struct clk *tclk; int i = 0, j = 0, reg; int op_cnt = 0; @@ -4642,6 +4736,13 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long esdhc2_clk[0].get_rate = _clk_esdhc2_get_rate; esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate; + esdhc1_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc2_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc3_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc4_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + + ata_clk[1].secondary = &ahb_max_clk; + clk_tree_init(); for (i = 0; i < ARRAY_SIZE(lookups); i++) { @@ -4716,7 +4817,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long */ clk_set_parent(&vpu_clk[0], &axi_a_clk); clk_set_parent(&vpu_clk[1], &axi_a_clk); - clk_set_parent(&gpu3d_clk, &axi_a_clk); + clk_set_parent(&gpu3d_clk[0], &axi_a_clk); clk_set_parent(&gpu2d_clk, &axi_a_clk); /* move cspi to 24MHz */ @@ -4886,9 +4987,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { - __iomem void *base; struct clk *tclk; - int i = 0, j = 0, reg; + int i = 0, reg; u32 pll1_rate; pll1_base = MX53_DPLL1_BASE; @@ -4957,6 +5057,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long vpu_clk[2].secondary = &emi_intr_clk[0]; + ata_clk[1].secondary = &tmax3_clk; + #if defined(CONFIG_USB_STATIC_IRAM) \ || defined(CONFIG_USB_STATIC_IRAM_PPH) usboh3_clk[1].secondary = &emi_intr_clk[1]; @@ -5118,7 +5220,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&arm_axi_clk, &axi_b_clk); clk_set_parent(&ipu_clk[0], &axi_b_clk); - clk_set_parent(&gpu3d_clk, &axi_b_clk); + clk_set_parent(&gpu3d_clk[0], &axi_b_clk); clk_set_parent(&gpu2d_clk, &axi_b_clk); clk_set_parent(&emi_slow_clk, &ahb_clk); @@ -5216,10 +5318,10 @@ static int cpu_clk_set_op(int op) getnstimeofday(&nstimeofday); do { getnstimeofday(&curtime); - if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) - panic("pll1 relock failed\n"); stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF; + if (((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) && (!stat)) + panic("pll1 relock failed\n"); } while (!stat); reg = __raw_readl(MXC_CCM_CCSR); @@ -5230,8 +5332,5 @@ static int cpu_clk_set_op(int op) cpu_curr_op = op; } -#if defined(CONFIG_CPU_FREQ) - cpufreq_trig_needed = 1; -#endif return 0; } diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 94a69be98e4a..4feddb0699b0 100755 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -118,7 +118,7 @@ late_initcall(mx51_neon_fixup); static int get_mx53_srev(void) { - void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); + void __iomem *iim_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); u32 rev = readl(iim_base + IIM_SREV) & 0xff; switch (rev) { @@ -283,6 +283,17 @@ static int __init post_cpu_init(void) reg = 0x8; __raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC); + if (cpu_is_mx53()) { + /*Allow for automatic gating of the EMI internal clock. + * If this is done, emi_intr CCGR bits should be set to 11. + */ + base = ioremap(MX53_M4IF_BASE_ADDR, SZ_4K); + reg = __raw_readl(base + 0x8c); + reg &= ~0x1; + __raw_writel(reg, base + 0x8c); + iounmap(base); + } + if (cpu_is_mx50()) init_ddr_settings(); diff --git a/arch/arm/mach-mx5/cpu_op-mx53.c b/arch/arm/mach-mx5/cpu_op-mx53.c index debe1bc411d4..8de811d1b19d 100755 --- a/arch/arm/mach-mx5/cpu_op-mx53.c +++ b/arch/arm/mach-mx5/cpu_op-mx53.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -49,7 +49,7 @@ static struct dvfs_op dvfs_core_setpoint_aec[] = { static struct dvfs_op dvfs_core_setpoint_ces_1_2G[] = { {33, 25, 33, 10, 10, 0x08}, /*1_2GHz*/ {30, 18, 33, 20, 10, 0x08}, /* 800MHz */ - {25, 8, 33, 20, 10, 0x08}, /* 400MHz */ + {25, 0, 33, 20, 10, 0x08}, /* 400MHz */ {28, 8, 33, 20, 30, 0x08}, /* 400MHZ, 133MHz */ {29, 0, 33, 20, 10, 0x08},}; /* 400MHZ, 50MHz. */ @@ -57,7 +57,7 @@ static struct dvfs_op dvfs_core_setpoint_ces_1_2G[] = { static struct dvfs_op dvfs_core_setpoint_ces[] = { {33, 25, 33, 10, 10, 0x08}, /*1GHz*/ {30, 18, 33, 20, 10, 0x08}, /* 800MHz */ - {25, 8, 33, 20, 10, 0x08}, /* 400MHz */ + {25, 0, 33, 20, 10, 0x08}, /* 400MHz */ {28, 8, 33, 20, 30, 0x08}, /* 400MHz, 133MHz */ {29, 0, 33, 20, 10, 0x08},}; /* 400MHz, 50MHz. */ @@ -71,7 +71,7 @@ static struct cpu_op cpu_op_aec[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1050000,}, + .cpu_voltage = 1100000,}, }; /* working point for consumer 1G*/ @@ -84,7 +84,7 @@ static struct cpu_op cpu_op_ces[] = { .mfd = 11, .mfn = 5, .cpu_podf = 0, - .cpu_voltage = 1200000,}, + .cpu_voltage = 1250000,}, { .pll_rate = 800000000, .cpu_rate = 800000000, @@ -93,17 +93,16 @@ static struct cpu_op cpu_op_ces[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1050000,}, + .cpu_voltage = 1100000,}, { .pll_rate = 800000000, .cpu_rate = 400000000, - .cpu_podf = 1, - .cpu_voltage = 950000,}, - { - .pll_rate = 800000000, - .cpu_rate = 160000000, - .cpu_podf = 4, - .cpu_voltage = 900000,}, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 1, + .cpu_voltage = 950000,}, }; /* working point for consumer 1.2G*/ @@ -118,15 +117,6 @@ static struct cpu_op cpu_op_ces_1_2g[] = { .cpu_podf = 0, .cpu_voltage = 1300000,}, { - .pll_rate = 1000000000, - .cpu_rate = 1000000000, - .pdf = 0, - .mfi = 10, - .mfd = 11, - .mfn = 5, - .cpu_podf = 0, - .cpu_voltage = 1200000,}, - { .pll_rate = 800000000, .cpu_rate = 800000000, .pdf = 0, @@ -134,17 +124,12 @@ static struct cpu_op cpu_op_ces_1_2g[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1050000,}, + .cpu_voltage = 1100000,}, { .pll_rate = 800000000, .cpu_rate = 400000000, .cpu_podf = 1, .cpu_voltage = 950000,}, - { - .pll_rate = 800000000, - .cpu_rate = 160000000, - .cpu_podf = 4, - .cpu_voltage = 900000,}, }; static struct dvfs_op *mx53_get_dvfs_core_table(int *wp) diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c32d19f6ddb9..fb53cbb4c95f 100755 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -492,6 +492,10 @@ /* MX53 */ #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9) #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6) #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0) @@ -787,18 +791,16 @@ #define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0) #define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300) -/* CORTEXA8 platform */ -extern void __iomem *arm_plat_base; -#define MXC_CORTEXA8_BASE (arm_plat_base) -#define MXC_CORTEXA8_PLAT_PVID (arm_plat_base + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (arm_plat_base + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (arm_plat_base + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (arm_plat_base + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (arm_plat_base + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (arm_plat_base + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (arm_plat_base + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (arm_plat_base + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (arm_plat_base + 0x24) +/* CORTEXA8 platform offsets */ +#define MXC_CORTEXA8_PLAT_PVID (0x0) +#define MXC_CORTEXA8_PLAT_GPC (0x4) +#define MXC_CORTEXA8_PLAT_PIC (0x8) +#define MXC_CORTEXA8_PLAT_LPC (0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (0x10) +#define MXC_CORTEXA8_PLAT_ICGC (0x14) +#define MXC_CORTEXA8_PLAT_AMC (0x18) +#define MXC_CORTEXA8_PLAT_NMC (0x20) +#define MXC_CORTEXA8_PLAT_NMS (0x24) /* DVFS CORE */ #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index 50b521461927..b8bf44f735a4 100755 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -48,6 +48,10 @@ extern const struct imx_ipuv3_data imx53_ipuv3_data __initconst; extern const struct imx_vpu_data imx53_vpu_data __initconst; #define imx53_add_vpu() imx_add_vpu(&imx53_vpu_data) +extern const struct imx_imx_asrc_data imx53_imx_asrc_data[] __initconst; +#define imx53_add_asrc(pdata) \ + imx_add_imx_asrc(imx53_imx_asrc_data, pdata) + extern const struct imx_tve_data imx53_tve_data __initconst; #define imx53_add_tve(pdata) \ imx_add_tve(&imx53_tve_data, pdata) @@ -86,7 +90,7 @@ extern const struct imx_iim_data imx53_imx_iim_data __initconst; #define imx53_add_iim(pdata) \ imx_add_iim(&imx53_imx_iim_data, pdata) -extern const struct imx_mxc_gpu_data imx53_gpu_data __initconst; +extern struct imx_mxc_gpu_data imx53_gpu_data __initconst; #define imx53_add_mxc_gpu(pdata) \ imx_add_mxc_gpu(&imx53_gpu_data, pdata) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index f6f3f68e26a8..b8573a514873 100755 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -1,6 +1,6 @@ /* * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -17,6 +17,16 @@ #include <mach/imx-uart.h> #include <mach/irqs.h> +struct platform_device mxc_android_pmem_device = { + .name = "android_pmem", + .id = 0, +}; + +struct platform_device mxc_android_pmem_gpu_device = { + .name = "android_pmem", + .id = 1, +}; + static struct resource mxc_hsi2c_resources[] = { { .start = MX51_HSI2C_DMA_BASE_ADDR, @@ -103,7 +113,7 @@ static struct resource usbotg_wakeup_resources[] = { }; struct platform_device mxc_usbdr_wakeup_device = { - .name = "usb_wakeup", + .name = "usb-wakeup", .id = 0, .num_resources = ARRAY_SIZE(usbotg_wakeup_resources), .resource = usbotg_wakeup_resources, @@ -167,7 +177,7 @@ static struct resource usbh1_wakeup_resources[] = { }; struct platform_device mxc_usbh1_wakeup_device = { - .name = "usb_wakeup", + .name = "usb-wakeup", .id = 1, .num_resources = ARRAY_SIZE(usbh1_wakeup_resources), .resource = usbh1_wakeup_resources, @@ -208,7 +218,7 @@ static struct resource usbh2_wakeup_resources[] = { }; struct platform_device mxc_usbh2_wakeup_device = { - .name = "usb_wakeup", + .name = "usb-wakeup", .id = 2, .num_resources = ARRAY_SIZE(usbh2_wakeup_resources), .resource = usbh2_wakeup_resources, diff --git a/arch/arm/mach-mx5/imx_bt_rfkill.c b/arch/arm/mach-mx5/imx_bt_rfkill.c index 372ba0fe769b..3c5a9d2caa6a 100755 --- a/arch/arm/mach-mx5/imx_bt_rfkill.c +++ b/arch/arm/mach-mx5/imx_bt_rfkill.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -109,6 +109,8 @@ static int imx_bt_rfkill_probe(struct platform_device *dev) goto error_rfk_alloc; } + rfkill_set_led_trigger_name(rfk, "mxc_bt"); + rc = rfkill_register(rfk); if (rc) goto error_rfkill; @@ -141,7 +143,7 @@ static int __devexit imx_bt_rfkill_remove(struct platform_device *dev) return 0; } -static struct platform_driver imx_bt_rfkill_drv = { +static struct platform_driver imx_bt_rfkill_driver = { .driver = { .name = "imx_bt_rfkill", }, @@ -152,14 +154,14 @@ static struct platform_driver imx_bt_rfkill_drv = { static int __init imx_bt_rfkill_init(void) { - return platform_driver_register(&imx_bt_rfkill_drv); + return platform_driver_register(&imx_bt_rfkill_driver); } module_init(imx_bt_rfkill_init); static void __exit imx_bt_rfkill_exit(void) { - platform_driver_unregister(&imx_bt_rfkill_drv); + platform_driver_unregister(&imx_bt_rfkill_driver); } module_exit(imx_bt_rfkill_exit); diff --git a/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c b/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c index ae39b8451c39..abbd9449321e 100755 --- a/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c +++ b/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,7 +39,7 @@ #include <mach/iomux-mx53.h> #include <mach/gpio.h> -#define DA9052_LDO(max, min, rname, suspend_mv) \ +#define DA9052_LDO(max, min, rname, suspend_mv, num_consumers, consumers) \ {\ .constraints = {\ .name = (rname), \ @@ -55,46 +55,56 @@ .disabled = 0, \ }, \ },\ + .num_consumer_supplies = (num_consumers), \ + .consumer_supplies = (consumers), \ } -/* currently the suspend_mv field here takes no effects for DA9053 +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vddgp", + } +}; + +/* currently the suspend_mv here takes no effects for DA9053 preset-voltage have to be done in the latest stage during suspend*/ static struct regulator_init_data da9052_regulators_init[] = { DA9052_LDO(DA9052_LDO1_VOLT_UPPER, - DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300), + DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300, 0, NULL), DA9052_LDO(DA9052_LDO2_VOLT_UPPER, - DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300), + DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300, 0, NULL), DA9052_LDO(DA9052_LDO34_VOLT_UPPER, - DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300), + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300, 0, NULL), DA9052_LDO(DA9052_LDO34_VOLT_UPPER, - DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775), + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800, 0, NULL), DA9052_LDO(DA9052_LDO9_VOLT_UPPER, - DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500), + DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200, 0, NULL), /* BUCKS */ DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, - DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850), + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850, + ARRAY_SIZE(sw1_consumers), sw1_consumers), DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, - DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950), + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950, + 0, NULL), DA9052_LDO(DA9052_BUCK_MEM_VOLT_UPPER, - DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500), + DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500, 0, NULL), DA9052_LDO(DA9052_BUCK_PERI_VOLT_UPPER, - DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500) + DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500, 0, NULL) }; - -#define MX53_SMD_WiFi_BT_PWR_EN (2*32 + 10) /*GPIO_3_10 */ +#define MX53_SMD_WiFi_BT_PWR_EN IMX_GPIO_NR(3, 10) /*GPIO_3_10 */ struct regulator_init_data wifi_bt_reg_initdata = { .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS, @@ -123,6 +133,7 @@ static struct platform_device wifi_bt_reg_device = { static struct regulator_consumer_supply sgtl5000_consumer[] = { REGULATOR_SUPPLY("VDDA", NULL), REGULATOR_SUPPLY("VDDIO", NULL), + REGULATOR_SUPPLY("VDDD", NULL), }; static struct regulator_init_data sgtl5000_reg_initdata = { @@ -179,6 +190,25 @@ static struct da9052_leds_platform_data da9052_gpio_leds = { }; +static struct da9052_bat_platform_data da9052_bat = { + .sw_temp_control_en = 0, + .monitoring_interval = 500, + .sw_bat_temp_threshold = 60, + .sw_junc_temp_threshold = 120, + .hysteresis_window_size = 1, + .current_monitoring_window = 10, + .bat_with_no_resistor = 62, + .bat_capacity_limit_low = 4, + .bat_capacity_full = 100, + .bat_capacity_limit_high = 70, + .chg_hysteresis_const = 89, + .hysteresis_reading_interval = 1000, + .hysteresis_no_of_reading = 10, + .filter_size = 4, + .bat_volt_cutoff = 2800, + .vbat_first_valid_detect_iteration = 3, +}; + static void da9052_init_ssc_cache(struct da9052 *da9052) { unsigned char cnt; @@ -280,7 +310,7 @@ static int __init smd_da9052_init(struct da9052 *da9052) /* s3c_gpio_setpull(DA9052_IRQ_PIN, S3C_GPIO_PULL_UP);*/ int ret; /* Set interrupt as LOW LEVEL interrupt source */ - set_irq_type(gpio_to_irq(MX53_SMD_DA9052_IRQ), IRQF_TRIGGER_LOW); + irq_set_irq_type(gpio_to_irq(MX53_SMD_DA9052_IRQ), IRQF_TRIGGER_LOW); da9052_init_ssc_cache(da9052); #ifdef CONFIG_SND_SOC_SGTL5000 @@ -297,7 +327,7 @@ static struct da9052_platform_data __initdata da9052_plat = { .regulators = da9052_regulators_init, .led_data = &da9052_gpio_leds, .tsi_data = &da9052_tsi, - /* .bat_data = &da9052_bat, */ + .bat_data = &da9052_bat, /* .gpio_base = GPIO_BOARD_START, */ }; diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c index 9240b7aec88d..be466c4bed3e 100755 --- a/arch/arm/mach-mx5/pm.c +++ b/arch/arm/mach-mx5/pm.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -46,9 +46,13 @@ static struct cpu_op *cpu_op_tbl; static int cpu_op_nr; static struct clk *cpu_clk; static struct mxc_pm_platform_data *pm_data; +static int databahn_mode; + +static void __iomem *pll1_base; #if defined(CONFIG_CPU_FREQ) static int org_freq; +extern int cpufreq_suspended; extern int set_cpu_freq(int wp); #endif @@ -58,6 +62,7 @@ struct clk *gpc_dvfs_clk; extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr); extern void mx50_suspend(u32 databahn_addr); extern struct cpu_op *(*get_cpu_op)(int *wp); +extern void __iomem *ccm_base; extern void __iomem *databahn_base; extern void da9053_suspend_cmd(void); extern void da9053_resume_dump(void); @@ -65,32 +70,9 @@ extern void pm_da9053_i2c_init(u32 base_addr); extern int iram_ready; void *suspend_iram_base; -void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL; +void (*suspend_in_iram)(void *param1, void *param2, void* param3) = NULL; void __iomem *suspend_param1; -#define TZIC_WAKEUP0_OFFSET 0x0E00 -#define TZIC_WAKEUP1_OFFSET 0x0E04 -#define TZIC_WAKEUP2_OFFSET 0x0E08 -#define TZIC_WAKEUP3_OFFSET 0x0E0C -#define GPIO7_0_11_IRQ_BIT (0x1<<11) - -static void mx53_smd_loco_irq_wake_fixup(void) -{ - void __iomem *tzic_base; - tzic_base = ioremap(MX53_TZIC_BASE_ADDR, SZ_4K); - if (NULL == tzic_base) { - pr_err("fail to map MX53_TZIC_BASE_ADDR\n"); - return; - } - __raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET); - __raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET); - __raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET); - /* only enable irq wakeup for da9053 */ - __raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET); - iounmap(tzic_base); - pr_debug("only da9053 irq is wakeup-enabled\n"); -} - static int mx5_suspend_enter(suspend_state_t state) { if (gpc_dvfs_clk == NULL) @@ -112,14 +94,38 @@ static int mx5_suspend_enter(suspend_state_t state) return -EAGAIN; if (state == PM_SUSPEND_MEM) { - local_flush_tlb_all(); - flush_cache_all(); + if (!cpu_is_mx53()) { + local_flush_tlb_all(); + flush_cache_all(); + } if (pm_data && pm_data->suspend_enter) pm_data->suspend_enter(); - - suspend_in_iram(suspend_param1); - + if (cpu_is_mx51() || cpu_is_mx53()) { + /* Run the suspend code from iRAM. */ + suspend_in_iram(suspend_param1, NULL, NULL); + + if (!cpu_is_mx53()) { + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + } + } else { + if (cpu_is_mx50()) { + /* Store the LPM mode of databanhn */ + databahn_mode = __raw_readl( + databahn_base + DATABAHN_CTL_REG20); + + /* Suspend now. */ + suspend_in_iram(databahn_base, + ccm_base, pll1_base); + + /* Restore the LPM databahn_mode. */ + __raw_writel(databahn_mode, + databahn_base + DATABAHN_CTL_REG20); + + } + } if (pm_data && pm_data->suspend_exit) pm_data->suspend_exit(); } else { @@ -137,7 +143,7 @@ static int mx5_suspend_enter(suspend_state_t state) static int mx5_suspend_prepare(void) { #if defined(CONFIG_CPU_FREQ) -#define MX53_SUSPEND_CPU_WP 1000000000 +#define MX53_SUSPEND_CPU_WP 400000000 struct cpufreq_freqs freqs; u32 suspend_wp = 0; org_freq = clk_get_rate(cpu_clk); @@ -155,6 +161,7 @@ static int mx5_suspend_prepare(void) freqs.cpu = 0; freqs.flags = 0; + cpufreq_suspended = 1; if (clk_get_rate(cpu_clk) != cpu_op_tbl[suspend_wp].cpu_rate) { set_cpu_freq(cpu_op_tbl[suspend_wp].cpu_rate); cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); @@ -177,6 +184,7 @@ static void mx5_suspend_finish(void) freqs.cpu = 0; freqs.flags = 0; + cpufreq_suspended = 0; if (org_freq != clk_get_rate(cpu_clk)) { set_cpu_freq(org_freq); @@ -221,34 +229,49 @@ static struct platform_driver mx5_pm_driver = { .probe = mx5_pm_probe, }; +#define SUSPEND_ID_MX51 1 +#define SUSPEND_ID_MX53 3 +#define SUSPEND_ID_NONE 4 static int __init pm_init(void) { - unsigned long iram_paddr, cpaddr; + unsigned long iram_paddr; + void *cpaddr; pr_info("Static Power Management for Freescale i.MX5\n"); if (platform_driver_register(&mx5_pm_driver) != 0) { printk(KERN_ERR "mx5_pm_driver register failed\n"); return -ENODEV; } + if (cpu_is_mx51()) + pll1_base = MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR); + else if (cpu_is_mx53()) + pll1_base = MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR); + else if (cpu_is_mx50()) + pll1_base = MX50_IO_ADDRESS(MX50_PLL1_BASE_ADDR); + + suspend_param1 = 0; suspend_set_ops(&mx5_suspend_ops); /* Move suspend routine into iRAM */ cpaddr = iram_alloc(SZ_4K, &iram_paddr); /* Need to remap the area here since we want the memory region to be executable. */ suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K, - MT_HIGH_VECTORS); - pr_info("cpaddr = %x suspend_iram_base=%x\n", cpaddr, suspend_iram_base); + MT_MEMORY_NONCACHED); + pr_info("cpaddr = %x suspend_iram_base=%x\n", (unsigned int)cpaddr, + (unsigned int)suspend_iram_base); if (cpu_is_mx51() || cpu_is_mx53()) { - suspend_param1 = MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR + 0x4b8); - memcpy(cpaddr, cpu_do_suspend_workaround, + suspend_param1 = + cpu_is_mx51() ? (void *)SUSPEND_ID_MX51: \ + (void *)SUSPEND_ID_MX53; + memcpy(suspend_iram_base, cpu_do_suspend_workaround, SZ_4K); } else if (cpu_is_mx50()) { /* * Need to run the suspend code from IRAM as the DDR needs * to be put into self refresh mode manually. */ - memcpy(cpaddr, mx50_suspend, SZ_4K); + memcpy(suspend_iram_base, mx50_suspend, SZ_4K); suspend_param1 = databahn_base; } diff --git a/arch/arm/mach-mx5/pm_da9053.c b/arch/arm/mach-mx5/pm_da9053.c new file mode 100644 index 000000000000..1313aa78d8c3 --- /dev/null +++ b/arch/arm/mach-mx5/pm_da9053.c @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/mfd/da9052/reg.h> + +#include <asm/mach-types.h> +#include <mach/hardware.h> +#include <mach/i2c.h> +#include "pmic.h" + +/** Defines ******************************************************************** +*******************************************************************************/ +/* have to hard-code the preset voltage here for they share the register +as the normal setting on Da9053 */ +/* preset buck core to 850 mv */ +#define BUCKCORE_SUSPEND_PRESET 0xCE +/* preset buck core to 950 mv */ +#define BUCKPRO_SUSPEND_PRESET 0xD2 +/* preset ldo6 to 1200 mv */ +#define LDO6_SUSPEND_PRESET 0xC0 +/* preset ldo10 to 1200 mv */ +#define iLDO10_SUSPEND_PRESET 0xC0 +/* set VUSB 2V5 active during suspend */ +#define BUCKPERI_SUSPEND_SW_STEP 0x50 +/* restore VUSB 2V5 active after suspend */ +#define BUCKPERI_RESTORE_SW_STEP 0x55 +/* restore VUSB 2V5 power supply after suspend */ +#define SUPPLY_RESTORE_VPERISW_EN 0x20 +#define CONF_BIT 0x80 + +#define DA9053_SLEEP_DELAY 0x1f +#define DA9052_CONTROLC_SMD_SET 0x62 +#define DA9052_GPIO0809_SMD_SET 0x18 +#define DA9052_ID1415_SMD_SET 0x1 +#define DA9052_GPI9_IRQ_MASK 0x2 +#define DA9052_ALARM_IRQ_EN (0x1<<6) +#define DA9052_SEQ_RDY_IRQ_MASK (0x1<<6) + +static u8 volt_settings[DA9052_LDO10_REG - DA9052_BUCKCORE_REG + 1]; + +static void pm_da9053_read_reg(u8 reg, u8 *value) +{ + unsigned char buf[2] = {0, 0}; + struct i2c_msg i2cmsg[2]; + buf[0] = reg; + i2cmsg[0].addr = 0x48 ; + i2cmsg[0].len = 1; + i2cmsg[0].buf = &buf[0]; + + i2cmsg[0].flags = 0; + + i2cmsg[1].addr = 0x48 ; + i2cmsg[1].len = 1; + i2cmsg[1].buf = &buf[1]; + + i2cmsg[1].flags = I2C_M_RD; + + pm_i2c_imx_xfer(i2cmsg, 2); + *value = buf[1]; +} + +static void pm_da9053_write_reg(u8 reg, u8 value) +{ + unsigned char buf[2] = {0, 0}; + struct i2c_msg i2cmsg[2]; + buf[0] = reg; + buf[1] = value; + i2cmsg[0].addr = 0x48 ; + i2cmsg[0].len = 2; + i2cmsg[0].buf = &buf[0]; + i2cmsg[0].flags = 0; + pm_i2c_imx_xfer(i2cmsg, 1); +} + +static void pm_da9053_preset_voltage(void) +{ + u8 reg, data; + for (reg = DA9052_BUCKCORE_REG; + reg <= DA9052_LDO10_REG; reg++) { + pm_da9053_read_reg(reg, &data); + volt_settings[reg - DA9052_BUCKCORE_REG] = data; + data |= CONF_BIT; + pm_da9053_write_reg(reg, data); + } + pm_da9053_write_reg(DA9052_BUCKCORE_REG, BUCKCORE_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_BUCKPRO_REG, BUCKPRO_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_LDO6_REG, LDO6_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_LDO10_REG, iLDO10_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_ID1213_REG, BUCKPERI_SUSPEND_SW_STEP); +} + +#if 0 +static void pm_da9053_dump(int start, int end) +{ + u8 reg, data; + for (reg = start; reg <= end; reg++) { + pm_da9053_read_reg(reg, &data); + pr_info("reg %u = 0x%2x\n", + reg, data); + } +} +#endif + +int da9053_suspend_cmd_sw(void) +{ + unsigned char buf[2] = {0, 0}; + struct clk *i2c_clk; + u8 data; + buf[0] = 29; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_preset_voltage(); + + pm_da9053_read_reg(DA9052_ID01_REG, &data); + data &= ~(DA9052_ID01_DEFSUPPLY | DA9052_ID01_nRESMODE); + pm_da9053_write_reg(DA9052_ID01_REG, data); + + pm_da9053_write_reg(DA9052_SEQB_REG, DA9053_SLEEP_DELAY); + + pm_da9053_read_reg(DA9052_CONTROLB_REG, &data); + data |= DA9052_CONTROLB_DEEPSLEEP; + pm_da9053_write_reg(DA9052_CONTROLB_REG, data); + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} + +int da9053_suspend_cmd_hw(void) +{ + unsigned char buf[2] = {0, 0}; + struct clk *i2c_clk; + u8 data; + buf[0] = 29; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_preset_voltage(); + pm_da9053_write_reg(DA9052_CONTROLC_REG, + DA9052_CONTROLC_SMD_SET); + + pm_da9053_read_reg(DA9052_ID01_REG, &data); + data &= ~(DA9052_ID01_DEFSUPPLY | DA9052_ID01_nRESMODE); + pm_da9053_write_reg(DA9052_ID01_REG, data); + + pm_da9053_write_reg(DA9052_GPIO0809_REG, + DA9052_GPIO0809_SMD_SET); + pm_da9053_read_reg(DA9052_IRQMASKD_REG, &data); + data |= DA9052_GPI9_IRQ_MASK; + pm_da9053_write_reg(DA9052_IRQMASKD_REG, data); +#ifdef CONFIG_RTC_DRV_DA9052 + pm_da9053_read_reg(DA9052_ALARMY_REG, &data); + data |= DA9052_ALARM_IRQ_EN; + pm_da9053_write_reg(DA9052_ALARMY_REG, data); +#endif + /* Mask SEQ_RDY_IRQ to avoid some suspend/resume issues */ + pm_da9053_read_reg(DA9052_IRQMASKA_REG, &data); + data |= DA9052_SEQ_RDY_IRQ_MASK; + pm_da9053_write_reg(DA9052_IRQMASKA_REG, data); + + pm_da9053_read_reg(DA9052_ID1415_REG, &data); + data &= 0xf0; + data |= DA9052_ID1415_SMD_SET; + pm_da9053_write_reg(DA9052_ID1415_REG, data); + + pm_da9053_write_reg(DA9052_SEQTIMER_REG, 0); + /* pm_da9053_write_reg(DA9052_SEQB_REG, 0x1f); */ + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} + +int da9053_restore_volt_settings(void) +{ + u8 data; + struct clk *i2c_clk; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_write_reg(DA9052_ID1213_REG, BUCKPERI_RESTORE_SW_STEP); + pm_da9053_read_reg(DA9052_SUPPLY_REG, &data); + data |= SUPPLY_RESTORE_VPERISW_EN; + pm_da9053_write_reg(DA9052_SUPPLY_REG, data); + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} diff --git a/arch/arm/mach-mx5/pm_i2c.c b/arch/arm/mach-mx5/pm_i2c.c new file mode 100644 index 000000000000..0b0525aa5aca --- /dev/null +++ b/arch/arm/mach-mx5/pm_i2c.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <asm/mach-types.h> +#include <mach/hardware.h> +#include <mach/i2c.h> + +/** Defines ******************************************************************** +*******************************************************************************/ + + +/* IMX I2C registers */ +#define IMX_I2C_IADR 0x00 /* i2c slave address */ +#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ +#define IMX_I2C_I2CR 0x08 /* i2c control */ +#define IMX_I2C_I2SR 0x0C /* i2c status */ +#define IMX_I2C_I2DR 0x10 /* i2c transfer data */ + +/* Bits of IMX I2C registers */ +#define I2SR_RXAK 0x01 +#define I2SR_IIF 0x02 +#define I2SR_SRW 0x04 +#define I2SR_IAL 0x10 +#define I2SR_IBB 0x20 +#define I2SR_IAAS 0x40 +#define I2SR_ICF 0x80 +#define I2CR_RSTA 0x04 +#define I2CR_TXAK 0x08 +#define I2CR_MTX 0x10 +#define I2CR_MSTA 0x20 +#define I2CR_IIEN 0x40 +#define I2CR_IEN 0x80 + +static void __iomem *base; +static int stopped; + +/** Functions for IMX I2C adapter driver *************************************** +*******************************************************************************/ + +static int pm_i2c_imx_bus_busy(int for_busy) +{ + unsigned int temp; + + while (1) { + temp = readb(base + IMX_I2C_I2SR); + if (for_busy && (temp & I2SR_IBB)) + break; + if (!for_busy && !(temp & I2SR_IBB)) + break; + pr_debug("waiting bus busy=%d\n", for_busy); + } + + return 0; +} + +static int pm_i2c_imx_trx_complete(void) +{ + unsigned int temp; + while (!((temp = readb(base + IMX_I2C_I2SR)) & I2SR_IIF)) + pr_debug("waiting or I2SR_IIF\n"); + temp &= ~I2SR_IIF; + writeb(temp, base + IMX_I2C_I2SR); + + return 0; +} + +static int pm_i2c_imx_acked(void) +{ + if (readb(base + IMX_I2C_I2SR) & I2SR_RXAK) { + pr_info("<%s> No ACK\n", __func__); + return -EIO; /* No ACK */ + } + return 0; +} + +static int pm_i2c_imx_start(void) +{ + unsigned int temp = 0; + int result; + + /* Enable I2C controller */ + writeb(0, base + IMX_I2C_I2SR); + writeb(I2CR_IEN, base + IMX_I2C_I2CR); + + /* Wait controller to be stable */ + udelay(50); + + /* Start I2C transaction */ + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_MSTA; + writeb(temp, base + IMX_I2C_I2CR); + result = pm_i2c_imx_bus_busy(1); + + temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + return result; +} + +static void pm_i2c_imx_stop(void) +{ + unsigned int temp = 0; + + /* Stop I2C transaction */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~(I2CR_MSTA | I2CR_MTX); + writeb(temp, base + IMX_I2C_I2CR); + + pm_i2c_imx_bus_busy(0); + + /* Disable I2C controller */ + writeb(0, base + IMX_I2C_I2CR); +} + +static int pm_i2c_imx_write(struct i2c_msg *msgs) +{ + int i, result; + + /* write slave address */ + writeb(msgs->addr << 1, base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + + /* write data */ + for (i = 0; i < msgs->len; i++) { + writeb(msgs->buf[i], base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + } + return 0; +} + +static int pm_i2c_imx_read(struct i2c_msg *msgs) +{ + int i, result; + unsigned int temp; + + /* write slave address */ + writeb((msgs->addr << 1) | 0x01, base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + + /* setup bus to read data */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~I2CR_MTX; + if (msgs->len - 1) + temp &= ~I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + readb(base + IMX_I2C_I2DR); /* dummy read */ + + /* read data */ + for (i = 0; i < msgs->len; i++) { + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + if (i == (msgs->len - 1)) { + /* It must generate STOP before read I2DR to prevent + controller from generating another clock cycle */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~(I2CR_MSTA | I2CR_MTX); + writeb(temp, base + IMX_I2C_I2CR); + pm_i2c_imx_bus_busy(0); + stopped = 1; + } else if (i == (msgs->len - 2)) { + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + } + msgs->buf[i] = readb(base + IMX_I2C_I2DR); + } + return 0; +} + +int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num) +{ + unsigned int i, temp; + int result; + + /* Start I2C transfer */ + result = pm_i2c_imx_start(); + if (result) + goto fail0; + + /* read/write data */ + for (i = 0; i < num; i++) { + if (i) { + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_RSTA; + writeb(temp, base + IMX_I2C_I2CR); + result = pm_i2c_imx_bus_busy(1); + if (result) + goto fail0; + } + /* write/read data */ + if (msgs[i].flags & I2C_M_RD) + result = pm_i2c_imx_read(&msgs[i]); + else + result = pm_i2c_imx_write(&msgs[i]); + if (result) + goto fail0; + } + +fail0: + /* Stop I2C transfer */ + pm_i2c_imx_stop(); + + return (result < 0) ? result : num; +} + +void pm_i2c_init(u32 base_addr) +{ + base = ioremap(base_addr, SZ_4K); +} + +void pm_i2c_deinit(void) +{ + iounmap(base); +} diff --git a/arch/arm/mach-mx5/pmic.h b/arch/arm/mach-mx5/pmic.h new file mode 100644 index 000000000000..72d7f6a42fe3 --- /dev/null +++ b/arch/arm/mach-mx5/pmic.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_PMIC_H__ +#define __ASM_ARCH_MACH_PMIC_H__ + +extern int __init mx53_loco_init_da9052(void); +extern int __init mx53_loco_init_mc34708(void); +extern int da9053_suspend_cmd_sw(void); +extern int da9053_suspend_cmd_hw(void); +extern int da9053_restore_volt_settings(void); +extern void pm_i2c_init(u32 base_addr); +extern int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num); + +#endif diff --git a/arch/arm/mach-mx5/suspend.S b/arch/arm/mach-mx5/suspend.S index c7937ec94d9f..a1059124664b 100755 --- a/arch/arm/mach-mx5/suspend.S +++ b/arch/arm/mach-mx5/suspend.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* * The code contained herein is licensed under the GNU General Public @@ -11,11 +11,72 @@ */ #include <linux/linkage.h> +#include <mach/hardware.h> +#include <mach/mx51.h> +#include <mach/mx53.h> #define ARM_CTRL_DCACHE 1 << 2 #define ARM_CTRL_ICACHE 1 << 12 #define ARM_AUXCR_L2EN 1 << 1 +.macro PM_SET_BACKUP_REG, addr, num + ldr r2, =\addr + ldr r2, [r1, r2] + str r2, [r3, #(\num * 4)] +.endm + +.macro PM_SET_HIGHZ_PAD, addr + ldr r2, =\addr + str r4, [r1, r2] +.endm + +.macro PM_SET_RESTORE_REG, addr, num + ldr r4, [r3, #(\num * 4)] + ldr r2, =\addr + str r4, [r1, r2] +.endm + +.macro PM_SET_ADDR_REG, addr, reg + mov \reg, #(\addr & 0x000000FF) + orr \reg, \reg, #(\addr & 0x0000FF00) + orr \reg, \reg, #(\addr & 0x00FF0000) + orr \reg, \reg, #(\addr & 0xFF000000) +.endm + +#define SUSPEND_ID_MX51 1 +#define SUSPEND_ID_MX53 3 +#define SUSPEND_ID_NONE 4 + +#define MX51_DRAM_SDCLK_PAD_CTRL_ADDR MX51_IO_ADDRESS(0x73FA84B8) +#define MX51_CCM_BASE MX51_IO_ADDRESS(0x73fd4000) +#define MX51_PLL1_BASE MX51_IO_ADDRESS(0x83f80000) + +#define M4IF_MCR0_OFFSET (0x008C) +#define M4IF_MCR0_FDVFS (0x1 << 11) +#define M4IF_MCR0_FDVACK (0x1 << 27) +#define IOMUXC_BASE_ADDR_VIRT MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR) +#define M4IF_BASE_ADDR_VIRT MX53_IO_ADDRESS(MX53_M4IF_BASE_ADDR) + +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x554 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x558 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x560 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x564 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x568 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x570 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x574 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x578 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x57c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x580 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x584 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x588 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x590 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x594 +#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x6f0 +#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x718 +#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x71c +#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x720 +#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x728 +#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x72c /* * cpu_do_suspend_workaround() @@ -27,7 +88,9 @@ ENTRY(cpu_do_suspend_workaround) stmfd sp!, {r4,r5,r6,r7,r9,r10,r11} @ Save registers - mov r6, r0 @save iomux address + mov r6, r0 @save iomux address + cmp r6, #SUSPEND_ID_MX51 + bne mx53_start @ don't disable cache on imx53 /* Disable L1 caches */ mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg bic r0, r0, #ARM_CTRL_ICACHE @ Disable ICache @@ -78,26 +141,253 @@ FinishedClean: bic r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg -#if 0 +mx53_start: + /* Do nothing for DDR */ + cmp r6, #SUSPEND_ID_NONE + beq mx5x_wfi /*Set the DDR drive strength to low */ - ldr r10, [r6] - and r10, r10, #0xF1 @ clear bits 2-1 - str r10, [r6] -#endif + cmp r6, #SUSPEND_ID_MX51 + bne mx53_reduce_ddr_drive_strength + ldr r0, =MX51_DRAM_SDCLK_PAD_CTRL_ADDR + ldr r1, [r0] + str r1, __mx5x_temp_stack + bic r1, r1, #0x6 + str r1, [r0] +mx53_reduce_ddr_drive_strength: + cmp r6, #SUSPEND_ID_MX53 + bne mx5x_wfi + +mx53_force_ddr_selfrefresh: + /* Point R0 at M4IF register set */ + ldr r0, =M4IF_BASE_ADDR_VIRT + + /* Point R1 at IOMUX register set */ + ldr r1, =IOMUXC_BASE_ADDR_VIRT + + /* Point R3 at temporary IRAM storage for DDR pad config */ + adr r3, __mx5x_temp_stack + + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, 0 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, 1 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, 2 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1, 3 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, 4 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1, 5 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, 6 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0, 7 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, 8 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0, 9 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, 10 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, 11 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, 12 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, 13 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_ADDDS, 14 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B0DS, 15 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B1DS, 16 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_CTLDS, 17 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B2DS, 18 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B3DS, 19 + + /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */ + ldr r2,[r0, #M4IF_MCR0_OFFSET] + orr r2, r2, #M4IF_MCR0_FDVFS + str r2,[r0, #M4IF_MCR0_OFFSET] + + /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */ +WAIT_SR_ACK: + ldr r2,[r0, #M4IF_MCR0_OFFSET] + ands r2, r2, #M4IF_MCR0_FDVACK + beq WAIT_SR_ACK + + /* + * Set DSE of all DDR I/O pads to 0 => HighZ + * except CKE which must drive during self-refresh + * according to JEDEC + */ + + ldr r4, =0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_ADDDS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B0DS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B1DS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B2DS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B3DS + /* use DSE=1 for CKE pin,when DDR is in self-refresh */ + ldr r4, =1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_CTLDS +mx5x_wfi: + /* + * PLL1 workaround as the following: For mx51 only. + * Before enter WFI + * (1) switch DDR and ARM to PLL2 + * (2) Disable AREN bit to avoid PLL1 restart during MFN change) + * (3) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179 + * thus the equation |MFN/(MFD+1)| < 1 + * (4) Manual restart PLL1 + * (5) Wait PLL1 lock + * After CPU out of WFI + * (6) Set PLL1 to 800Mhz with only change MFN to 60, others keep + * (7) Wait MFN change complete by delay 4.6us, + * (8) Switch DDR and ARM back to PLL1 + */ + cmp r6, #SUSPEND_ID_MX51 + + bne WFI + PM_SET_ADDR_REG MX51_PLL1_BASE, r3 + PM_SET_ADDR_REG MX51_CCM_BASE, r4 + + /* step 1 */ + ldr r0, [r4, #0x14] + bic r0, r0, #(0x1 << 30) + str r0, [r4, #0x14] + +1: + ldr r0, [r4, #0x48] + ands r0, r0, #(1 << 8) + bne 1b + + ldr r0, [r4, #0x0c] + bic r0, r0, #(0xf << 5) + orr r0, r0, #(0x1 << 8) + str r0, [r4, #0x0c] + + orr r0, r0, #(1 << 2) + str r0, [r4, #0x0c] + + /* step 2 */ + ldr r0, [r3, #0x4] + bic r0, r0, #0x2 + str r0, [r3, #0x4] /* disable auto-restart AREN bit */ + + /* step 3 */ + mov r0, #0x80 + mov r1, #179 + mov r2, #180 + str r0, [r3, #0x08] + str r0, [r3, #0x1c] + + str r1, [r3, #0x0c] + str r1, [r3, #0x20] + + str r2, [r3, #0x10] + str r2, [r3, #0x24] + + /* step 4 */ + ldr r0, =0x00001236 /* Set PLM =1, manual restart and enable PLL*/ + str r0, [r3, #0x0] +1: ldr r0, [r3, #0x0] + ands r0, r0, #0x1 + beq 1b +WFI: + mov r0,#0x0 + .long 0xe320f003 @ Opcode for WFI + + cmp r6, #SUSPEND_ID_MX51 + bne wfi_done + + /* step 5 */ + ldr r0, =60 + str r0, [r3, #0x10] + + /* step 6 */ + /* Load MFN by setting LDREQ */ + ldr r0, [r3, #0x04] + orr r0, r0, #0x1 + str r0, [r3, #0x04] + + /* Wait for LDREQ bit to clear. */ +2: ldr r0, [r3, #0x4] + tst r0, #1 + bne 2b + + mov r0, #100 /* delay more than 4.6 us */ +3: subs r0, r0, #1 + bge 3b + + /* step 8 */ + ldr r0, [r4, #0x0c] + bic r0, r0, #(1 << 2) + str r0, [r4, #0x0c] + + /* Source step_clk from LPAPM. */ + ldr r0, [r4, #0x0c] + bic r0, r0, #(3 << 7) + str r0, [r4, #0x0c] + + ldr r0, [r4, #0x14] + orr r0, r0, #(0x1 << 30) + str r0, [r4, #0x14] + +3: + ldr r0, [r4, #0x48] + ands r0, r0, #(1 << 8) + bne 3b + +wfi_done: + cmp r6, #SUSPEND_ID_NONE + beq mx5x_post_wfi + + /*Set the DDR drive strength to max */ + cmp r6, #SUSPEND_ID_MX51 + bne mx53_restore_ddr_drive_strength + ldr r0, =MX51_DRAM_SDCLK_PAD_CTRL_ADDR + ldr r1, __mx5x_temp_stack + str r1, [r0] +mx53_restore_ddr_drive_strength: + cmp r6, #SUSPEND_ID_MX53 + bne mx5x_post_wfi - .long 0xe320f003 @ Opcode for WFI + ldr r0, =M4IF_BASE_ADDR_VIRT + ldr r1, =IOMUXC_BASE_ADDR_VIRT + adr r3, __mx5x_temp_stack + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, 0 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, 1 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, 2 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1, 3 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, 4 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1, 5 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, 6 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0, 7 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, 8 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0, 9 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, 10 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, 11 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, 12 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, 13 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_ADDDS, 14 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B0DS, 15 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B1DS, 16 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_CTLDS, 17 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B2DS, 18 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B3DS, 19 -#if 0 - /*Set the DDR drive strength to max */ - orr r10, r10, #0x06 @ set bits 2-1 - str r10, [r6] -#endif + /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */ + ldr r2,[r0, #M4IF_MCR0_OFFSET] + bic r2, r2, #M4IF_MCR0_FDVFS + str r2,[r0, #M4IF_MCR0_OFFSET] - ldr r11, =0x0000fFFF -TestLoop: - subs r11,r11, #1 @ Decrement the index - bge TestLoop + /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */ +WAIT_AR_ACK: + ldr r2,[r0, #M4IF_MCR0_OFFSET] + ands r2, r2, #M4IF_MCR0_FDVACK + bne WAIT_AR_ACK + cmp r6, #SUSPEND_ID_MX51 + bne mx53_end +mx5x_post_wfi: mov r0, #0 mcr p15, 0, r0, c7, c5, 0 @ Invalidate inst cache @@ -152,9 +442,12 @@ FinishedInvalidate: orr r0, r0, #ARM_CTRL_DCACHE @ Enable DCache mcr p15, 0, r0, c1, c0, 0 @ Update system control reg +mx53_end: /* Restore registers */ ldmfd sp!, {r4,r5,r6,r7,r9,r10,r11} mov pc, lr +__mx5x_temp_stack: + .space 128 .type cpu_do_suspend, #object ENTRY(cpu_do_suspend) diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 70667446cff3..7a6918089e71 100755 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -47,34 +47,41 @@ extern int dvfs_core_is_active; extern void __iomem *ccm_base; extern void __iomem *databahn_base; extern int low_bus_freq_mode; -extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); +extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr, + u32 sys_clk_count); extern void mx50_wait(u32 ccm_base, u32 databahn_addr); extern void stop_dvfs(void); extern void *wait_in_iram_base; extern void __iomem *apll_base; +extern void __iomem *arm_plat_base; +extern void (*suspend_in_iram)(void *param1, void *param2, void* param3); +extern void __iomem *suspend_param1; static struct clk *gpc_dvfs_clk; -static struct regulator *vpll; static struct clk *pll1_sw_clk; static struct clk *osc; static struct clk *pll1_main_clk; static struct clk *ddr_clk ; -static int dvfs_core_paused; +static struct clk *sys_clk ; /* set cpu low power mode before WFI instruction */ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) { u32 plat_lpc, arm_srpgcr, ccm_clpcr; - u32 empgc0, empgc1; + u32 empgc0 = 0, empgc1 = 0; int stop_mode = 0; /* always allow platform to issue a deep sleep mode request */ - plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & + plat_lpc = __raw_readl(arm_plat_base + MXC_CORTEXA8_PLAT_LPC) & ~(MXC_CORTEXA8_PLAT_LPC_DSM); ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); + if (!cpu_is_mx53()) { + empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & + ~(MXC_SRPGCR_PCR); + empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & + ~(MXC_SRPGCR_PCR); + } switch (mode) { case WAIT_CLOCKED: @@ -111,7 +118,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) return; } - __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); + __raw_writel(plat_lpc, arm_plat_base + MXC_CORTEXA8_PLAT_LPC); __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); @@ -119,7 +126,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) if (mx50_revision() != IMX_CHIP_REVISION_1_0) __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); - if (stop_mode) { + if (stop_mode && !cpu_is_mx53()) { empgc0 |= MXC_SRPGCR_PCR; empgc1 |= MXC_SRPGCR_PCR; @@ -149,6 +156,9 @@ void arch_idle(void) mxc_cpu_lp_set(arch_idle_mode); if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) { + if (sys_clk == NULL) + sys_clk = clk_get(NULL, "sys_clk"); + memcpy(wait_in_iram_base, mx50_wait, SZ_4K); wait_in_iram = (void *)wait_in_iram_base; if (low_bus_freq_mode) { @@ -178,7 +188,8 @@ void arch_idle(void) cpu_podf = __raw_readl(MXC_CCM_CACRR); __raw_writel(0x01, MXC_CCM_CACRR); - wait_in_iram(ccm_base, databahn_base); + wait_in_iram(ccm_base, databahn_base, + clk_get_usecount(sys_clk)); /* Set the ARM-POD divider back * to the original. @@ -186,7 +197,11 @@ void arch_idle(void) __raw_writel(cpu_podf, MXC_CCM_CACRR); clk_set_parent(pll1_sw_clk, pll1_main_clk); } else - wait_in_iram(ccm_base, databahn_base); + wait_in_iram(ccm_base, databahn_base, + clk_get_usecount(sys_clk)); + } else if (cpu_is_mx53() && (clk_get_usecount(ddr_clk) == 0) + && low_bus_freq_mode) { + suspend_in_iram(suspend_param1, NULL, NULL); } else cpu_do_idle(); clk_disable(gpc_dvfs_clk); @@ -272,7 +287,7 @@ static int __mxs_reset_block(void __iomem *hwreg, int just_enable) int mxs_reset_block(void __iomem *hwreg, int just_enable) { int try = 10; - int r; + int r = 0; while (try--) { r = __mxs_reset_block(hwreg, just_enable); @@ -282,3 +297,4 @@ int mxs_reset_block(void __iomem *hwreg, int just_enable) } return r; } + diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 8933cacb8cb3..63b5fadd4d39 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -198,7 +198,9 @@ static int mxc_audmux_v2_init(void) if (cpu_is_mx51()) { audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR); ret = 0; - return ret; + } else if (cpu_is_mx53()) { + audmux_base = MX53_IO_ADDRESS(MX53_AUDMUX_BASE_ADDR); + ret = 0; } #endif #if defined(CONFIG_ARCH_MX3) diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 43d33376b52d..01035622f2be 100755 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -58,6 +58,7 @@ extern int low_freq_bus_used(void); static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); +static DEFINE_SPINLOCK(clockfw_lock); /*------------------------------------------------------------------------- * Standard clock functions defined in include/linux/clk.h @@ -101,7 +102,7 @@ static int __clk_enable(struct clk *clk) */ int clk_enable(struct clk *clk) { - /* unsigned long flags; */ + unsigned long flags; int ret = 0; if (in_interrupt()) { @@ -117,7 +118,7 @@ int clk_enable(struct clk *clk) lp_high_freq++; else if (clk->flags & AHB_MED_SET_POINT) lp_med_freq++; - else if (clk->flags & AHB_AUDIO_SET_POINT) + else if (cpu_is_mx6() && (clk->flags & AHB_AUDIO_SET_POINT)) lp_audio_freq++; if ((clk->flags & CPU_FREQ_TRIG_UPDATE) @@ -125,7 +126,7 @@ int clk_enable(struct clk *clk) if (!(clk->flags & (AHB_HIGH_SET_POINT | AHB_MED_SET_POINT))) { if (low_freq_bus_used()) { - if ((clk->flags & AHB_AUDIO_SET_POINT) & !audio_bus_freq_mode) + if (cpu_is_mx6() && (clk->flags & AHB_AUDIO_SET_POINT) & !audio_bus_freq_mode) set_low_bus_freq(); else if (!low_bus_freq_mode) set_low_bus_freq(); @@ -143,9 +144,10 @@ int clk_enable(struct clk *clk) set_high_bus_freq(1); } } - mutex_lock(&clocks_mutex); + + spin_lock_irqsave(&clockfw_lock, flags); ret = __clk_enable(clk); - mutex_unlock(&clocks_mutex); + spin_unlock_irqrestore(&clockfw_lock, flags); return ret; } @@ -157,7 +159,7 @@ EXPORT_SYMBOL(clk_enable); */ void clk_disable(struct clk *clk) { - /* unsigned long flags; */ + unsigned long flags; if (in_interrupt()) { printk(KERN_ERR " clk_disable cannot be called in an interrupt context\n"); @@ -172,12 +174,13 @@ void clk_disable(struct clk *clk) lp_high_freq--; else if (clk->flags & AHB_MED_SET_POINT) lp_med_freq--; - else if (clk->flags & AHB_AUDIO_SET_POINT) + else if (cpu_is_mx6() && (clk->flags & AHB_AUDIO_SET_POINT)) lp_audio_freq--; - mutex_lock(&clocks_mutex); + spin_lock_irqsave(&clockfw_lock, flags); __clk_disable(clk); - mutex_unlock(&clocks_mutex); + spin_unlock_irqrestore(&clockfw_lock, flags); + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) && (clk_get_usecount(clk) == 0)) { if (low_freq_bus_used() && !low_bus_freq_mode) @@ -244,14 +247,15 @@ EXPORT_SYMBOL(clk_round_rate); */ int clk_set_rate(struct clk *clk, unsigned long rate) { + unsigned long flags; int ret = -EINVAL; if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) return ret; - mutex_lock(&clocks_mutex); + spin_lock_irqsave(&clockfw_lock, flags); ret = clk->set_rate(clk, rate); - mutex_unlock(&clocks_mutex); + spin_unlock_irqrestore(&clockfw_lock, flags); return ret; } @@ -260,6 +264,7 @@ EXPORT_SYMBOL(clk_set_rate); /* Set the clock's parent to another clock source */ int clk_set_parent(struct clk *clk, struct clk *parent) { + unsigned long flags; int ret = -EINVAL; struct clk *old; @@ -270,7 +275,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) if (clk->usecount) clk_enable(parent); - mutex_lock(&clocks_mutex); + spin_lock_irqsave(&clockfw_lock, flags); ret = clk->set_parent(clk, parent); if (ret == 0) { old = clk->parent; @@ -278,7 +283,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) } else { old = parent; } - mutex_unlock(&clocks_mutex); + spin_unlock_irqrestore(&clockfw_lock, flags); if (clk->usecount) clk_disable(old); diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index 9dfdd39be28c..83b1a6c812d6 100755 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -34,6 +34,7 @@ static int cpu_freq_khz_min; static int cpu_freq_khz_max; +int cpufreq_suspended; static struct clk *cpu_clk; static struct cpufreq_frequency_table *imx_freq_table; @@ -131,7 +132,7 @@ static int mxc_set_target(struct cpufreq_policy *policy, if (policy->cpu > num_cpus) return 0; - if (dvfs_core_is_active) { + if (dvfs_core_is_active || cpufreq_suspended) { struct cpufreq_freqs freqs; freqs.old = policy->cur; @@ -182,19 +183,11 @@ static int mxc_set_target(struct cpufreq_policy *policy, static int mxc_cpufreq_suspend(struct cpufreq_policy *policy) { - pre_suspend_rate = clk_get_rate(cpu_clk); - /* Set to max freq and voltage */ - if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000)) - set_cpu_freq(imx_freq_table[0].frequency); - return 0; } static int mxc_cpufreq_resume(struct cpufreq_policy *policy) { - if (clk_get_rate(cpu_clk) != pre_suspend_rate) - set_cpu_freq(pre_suspend_rate); - return 0; } @@ -263,8 +256,8 @@ static int __devinit mxc_cpufreq_init(struct cpufreq_policy *policy) ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); if (ret < 0) { - printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n", - __func__, ret); + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq \ + with error code %d\n", __func__, ret); goto err; } diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 65a71ac8b9e9..19c31164c175 100755 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -54,7 +54,7 @@ struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = #ifdef CONFIG_SOC_IMX53 struct imx_imx_sdma_data imx53_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX53, 2, "imx53", 1); -#endif /* ifdef CONFIG_SOC_IMX51 */ +#endif /* ifdef CONFIG_SOC_IMX53 */ #ifdef CONFIG_SOC_IMX6Q struct imx_imx_sdma_data imx6q_imx_sdma_data __initconst = @@ -160,6 +160,8 @@ static struct sdma_script_start_addrs addr_imx51_to3 = { .app_2_mcu_addr = 683, .shp_2_per_addr = 1251, .shp_2_mcu_addr = 892, + .mcu_2_ssish_addr = 6600, + .ssish_2_mcu_addr = 6783, }; #endif @@ -175,6 +177,8 @@ static struct sdma_script_start_addrs addr_imx53_to1 = { .shp_2_mcu_addr = 891, .spdif_2_mcu_addr = 1100, .mcu_2_spdif_addr = 1134, + .mcu_2_ssish_addr = 6242, + .ssish_2_mcu_addr = 6679, }; #endif diff --git a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c index 06ac1560216a..526d5958c443 100755 --- a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -30,6 +30,8 @@ .iobase_2d = soc ## _GPU2D_BASE_ADDR, \ .gmem_base = soc ## _GPU_GMEM_BASE_ADDR, \ .gmem_size = soc ## _GPU_GMEM_SIZE, \ + .gmem_reserved_base = 0, \ + .gmem_reserved_size = SZ_128M, \ } #define imx_mxc_gpu_entry_2d(soc) \ @@ -54,7 +56,7 @@ const struct imx_mxc_gpu_data imx51_gpu_data __initconst = #endif #ifdef CONFIG_SOC_IMX53 -const struct imx_mxc_gpu_data imx53_gpu_data __initconst = +struct imx_mxc_gpu_data imx53_gpu_data = imx_mxc_gpu_entry_3d_2d(MX53); #endif @@ -93,6 +95,13 @@ struct platform_device *__init imx_add_mxc_gpu( .name = "gpu_graphics_mem", .flags = IORESOURCE_MEM, }, + { + .start = data->gmem_reserved_base, + .end = data->gmem_reserved_base + + data->gmem_reserved_size - 1, + .name = "gpu_reserved_mem", + .flags = IORESOURCE_MEM, + }, }; return imx_add_platform_device_dmamask("mxc_gpu", 0, diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c index d52f7b6eb039..6090251dffd0 100755 --- a/arch/arm/plat-mxc/dvfs_core.c +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -84,7 +84,7 @@ #define CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER 0x4 #define CCM_CDHIPR_ARM_PODF_BUSY 0x10000 -int cpufreq_trig_needed; +static int cpufreq_trig_needed; int dvfs_core_is_active; static struct mxc_dvfs_platform_data *dvfs_data; static struct device *dvfs_dev; @@ -114,6 +114,7 @@ static struct delayed_work dvfs_core_handler; */ static struct clk *pll1_sw_clk; static struct clk *cpu_clk; +static struct clk *gpu_clk; static struct clk *dvfs_clk; static int cpu_op_nr; @@ -189,6 +190,7 @@ static int mx5_set_cpu_freq(int op) int podf; int vinc = 0; int ret = 0; + int retry_count = 0; int org_cpu_rate; unsigned long rate = 0; int gp_volt = 0; @@ -257,6 +259,7 @@ static int mx5_set_cpu_freq(int op) udelay(10); spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + clk_set_rate(cpu_clk, rate); if (rate < org_cpu_rate) { ret = regulator_set_voltage(cpu_regulator, gp_volt, gp_volt); @@ -271,11 +274,19 @@ static int mx5_set_cpu_freq(int op) reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); reg &= ~(CCM_CDCR_SW_DVFS_EN); reg |= en_sw_dvfs; - clk_set_rate(cpu_clk, rate); } else { podf = cpu_op_tbl[op].cpu_podf; gp_volt = cpu_op_tbl[op].cpu_voltage; + /* Get ARM_PODF */ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset); + arm_podf = reg & 0x07; + if (podf == arm_podf) { + printk(KERN_DEBUG + "No need to change freq and voltage!!!!\n"); + return 0; + } + /* Change arm_podf only */ /* set ARM_FREQ_SHIFT_DIVIDER */ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); @@ -290,14 +301,6 @@ static int mx5_set_cpu_freq(int op) reg |= CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER; __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); - /* Get ARM_PODF */ - reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset); - arm_podf = reg & 0x07; - if (podf == arm_podf) { - printk(KERN_DEBUG - "No need to change freq and voltage!!!!\n"); - return 0; - } /* Check if FSVAI indicate freq up */ if (podf < arm_podf) { ret = regulator_set_voltage(cpu_regulator, gp_volt, @@ -355,7 +358,10 @@ static int mx5_set_cpu_freq(int op) /* Wait for arm podf Enable */ while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) & MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) { - printk(KERN_DEBUG "Waiting arm_podf enabled!\n"); + if (retry_count) + printk(KERN_DEBUG "Waiting arm_podf enabled!\n"); + + retry_count++; udelay(10); } spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); @@ -577,6 +583,7 @@ static irqreturn_t dvfs_irq(int irq, void *dev_id) return IRQ_HANDLED; } +extern int clk_get_usecount(struct clk *clk); static void dvfs_core_work_handler(struct work_struct *work) { u32 fsvai; @@ -584,8 +591,11 @@ static void dvfs_core_work_handler(struct work_struct *work) u32 curr_cpu = 0; int ret = 0; int low_freq_bus_ready = 0; + int disable_dvfs_irq = 0; int bus_incr = 0, cpu_dcr = 0; +#ifdef CONFIG_CPU_FREQ int cpu; +#endif low_freq_bus_ready = low_freq_bus_used(); @@ -598,6 +608,29 @@ static void dvfs_core_work_handler(struct work_struct *work) goto END; } curr_cpu = clk_get_rate(cpu_clk); + + if (clk_get_usecount(gpu_clk)) { + maxf = 1; + if (curr_cpu != cpu_op_tbl[0].cpu_rate) { + curr_op = 0; + minf = 0; + dvfs_load_config(0); + if (!high_bus_freq_mode) + set_high_bus_freq(1); + set_cpu_freq(curr_op); + } + /* If we enable DVFS's irq, the irq will keep coming, + * and will consume about 3-40% cpu usage, we disable + * dvfs 's irq here, and let it check the status every + * 100 msecs. If gpu clk have count to 0, it will + * enable dvfs's irq let it do what it want.*/ + schedule_delayed_work(&dvfs_core_handler, + msecs_to_jiffies(100)); + disable_dvfs_irq = 1; + goto END; + } else + disable_dvfs_irq = 0; + /* If FSVAI indicate freq down, check arm-clk is not in lowest frequency*/ if (fsvai == FSVAI_FREQ_DECREASE) { @@ -687,8 +720,10 @@ END: /* Enable DVFS interrupt */ /* FSVAIM=0 */ - reg = (reg & ~MXC_DVFSCNTR_FSVAIM); - reg |= FSVAI_FREQ_NOCHANGE; + if (!disable_dvfs_irq) { + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + reg |= FSVAI_FREQ_NOCHANGE; + } /* LBFL=1 */ reg = (reg & ~MXC_DVFSCNTR_LBFL); reg |= MXC_DVFSCNTR_LBFL; @@ -709,7 +744,10 @@ void stop_dvfs(void) u32 reg = 0; unsigned long flags; u32 curr_cpu; + u32 old_loops_per_jiffy; +#ifdef CONFIG_CPU_FREQ int cpu; +#endif if (dvfs_core_is_active) { @@ -736,7 +774,7 @@ void stop_dvfs(void) dvfs_cpu_jiffies(per_cpu(cpu_data, cpu).loops_per_jiffy, curr_cpu/1000, clk_get_rate(cpu_clk) / 1000); #else - u32 old_loops_per_jiffy = loops_per_jiffy; + old_loops_per_jiffy = loops_per_jiffy; loops_per_jiffy = dvfs_cpu_jiffies(old_loops_per_jiffy, @@ -748,6 +786,8 @@ void stop_dvfs(void) for (cpu = 0; cpu < num_online_cpus(); cpu++) cpufreq_get(cpu); #endif + if (cpufreq_trig_needed == 1) + cpufreq_trig_needed = 0; } spin_lock_irqsave(&mxc_dvfs_core_lock, flags); @@ -947,10 +987,18 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); return PTR_ERR(cpu_clk); } - if (!(cpu_is_mx6q() || cpu_is_mx6dl())) { + if (!cpu_is_mx6q()) { + gpu_clk = clk_get(NULL, "gpu3d_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get gpu clock\n", + __func__); + return PTR_ERR(gpu_clk); + } + dvfs_clk = clk_get(NULL, dvfs_data->clk2_id); if (IS_ERR(dvfs_clk)) { - printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__); + printk(KERN_ERR "%s: failed to get dvfs clock\n", + __func__); return PTR_ERR(dvfs_clk); } } diff --git a/arch/arm/plat-mxc/include/mach/check_fuse.h b/arch/arm/plat-mxc/include/mach/check_fuse.h new file mode 100644 index 000000000000..00c6116a8209 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/check_fuse.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ARCH_ARM_MACH_MX5_FUSE_CHECK_H__ +#define __ARCH_ARM_MACH_MX5_FUSE_CHECK_H__ + +#define MXC_IIM_MX5_DISABLERS_OFFSET 0x8 +#define MXC_IIM_MX5_DISABLERS_GPU_MASK 0x4 +#define MXC_IIM_MX5_DISABLERS_GPU_SHIFT 0x2 +#define MXC_IIM_MX5_DISABLERS_VPU_MASK 0x2 +#define MXC_IIM_MX5_DISABLERS_VPU_SHIFT 0x1 + +#define FSL_OCOTP_MX5_CFG2_OFFSET 0x060 +#define FSL_OCOTP_MX5_DISABLERS_GPU_MASK 0x2000000 +#define FSL_OCOTP_MX5_DISABLERS_GPU_SHIFT 0x19 + +int mxc_fuse_get_gpu_status(void); +int mxc_fuse_get_vpu_status(void); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 89bc884873f8..5cc9d626af15 100755 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -88,7 +88,7 @@ extern int mx53_revision(void); extern int mx50_revision(void); extern int mx53_display_revision(void); extern unsigned long mx6_timer_rate(void); -extern int mxs_reset_block(void __iomem *); +extern int mxs_reset_block(void __iomem *, int); extern void early_console_setup(unsigned long base, struct clk *clk); extern void mx6_cpu_regulator_init(void); extern int mx6q_sabreauto_init_pfuze100(u32 int_gpio); diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 6fce8c4b8255..ad27f5343ac4 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -411,6 +411,8 @@ struct imx_mxc_gpu_data { resource_size_t iobase_3d; resource_size_t gmem_base; resource_size_t gmem_size; + resource_size_t gmem_reserved_base; + resource_size_t gmem_reserved_size; }; struct platform_device *__init imx_add_mxc_gpu( diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 56bade10d581..4c12dc42df77 100755 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -870,7 +870,7 @@ #define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0) #define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0) #define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0) +#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0, 0, 0) #define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0) #define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0) #define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0) diff --git a/arch/arm/plat-mxc/include/mach/ipu-v3.h b/arch/arm/plat-mxc/include/mach/ipu-v3.h index 1ddd69ed1bb1..3965f00a3598 100755 --- a/arch/arm/plat-mxc/include/mach/ipu-v3.h +++ b/arch/arm/plat-mxc/include/mach/ipu-v3.h @@ -731,6 +731,8 @@ struct ipuv3_fb_platform_data { /* reserved mem */ resource_size_t res_base[2]; resource_size_t res_size[2]; + int panel_width_mm; /* Display panel width in millimeters */ + int panel_height_mm; /* Display panel height in millimeters */ }; struct imx_ipuv3_platform_data { diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 1bcddd633532..83f013706998 100755 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -221,6 +221,12 @@ #define MX53_DMA_REQ_ASRC_DMA3 34 #define MX53_DMA_REQ_ASRC_DMA2 33 #define MX53_DMA_REQ_ASRC_DMA1 32 +#define MX53_DMA_REQ_ASRC_TX3 37 +#define MX53_DMA_REQ_ASRC_TX2 36 +#define MX53_DMA_REQ_ASRC_TX1 35 +#define MX53_DMA_REQ_ASRC_RX3 34 +#define MX53_DMA_REQ_ASRC_RX2 33 +#define MX53_DMA_REQ_ASRC_RX1 32 #define MX53_DMA_REQ_EMI_WR 31 #define MX53_DMA_REQ_EMI_RD 30 #define MX53_DMA_REQ_SSI1_TX0 29 @@ -323,7 +329,8 @@ #define MX53_INT_I2C2 63 #define MX53_INT_I2C3 64 #define MX53_INT_RESV65 65 -#define MX53_INT_RESV66 66 +#define MX53_INT_ASRC 66 +/*#define MX53_INT_RESV66 66*/ #define MX53_INT_SPDIF 67 #define MX53_INT_SIM_DAT 68 #define MX53_INT_IIM 69 diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 6e7dfcc6e3b3..43b88c8a03b1 100755 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -70,6 +70,7 @@ #define IMX_BOARD_REV_2 0x100 #define IMX_BOARD_REV_3 0x200 #define IMX_BOARD_REV_4 0x300 +#define IMX_BOARD_REV_5 0x400 #ifndef __ASSEMBLY__ extern unsigned int system_rev; diff --git a/arch/arm/plat-mxc/include/mach/mxc_gpu.h b/arch/arm/plat-mxc/include/mach/mxc_gpu.h index a43d6ec99bfa..fbd87c6416db 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_gpu.h +++ b/arch/arm/plat-mxc/include/mach/mxc_gpu.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -17,8 +17,7 @@ struct mxc_gpu_platform_data { int z160_revision; - resource_size_t reserved_mem_base; - resource_size_t reserved_mem_size; + int enable_mmu; }; #endif /* __MACH_MXC_GPU_H_ */ diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 4a67f4de0e4d..5effdb3d6d3e 100755 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -6,7 +6,7 @@ * published by the Free Software Foundation. * * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> - * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ #include <linux/module.h> diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index cadf3bb23275..a76e49321173 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -1,7 +1,7 @@ /* * Copyright (C) 1999 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright 2006-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2012 Freescale Semiconductor, Inc. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com * @@ -21,17 +21,22 @@ #include <linux/io.h> #include <linux/err.h> #include <linux/delay.h> + +#include <asm/mach-types.h> +#include <mach/iomux-mx53.h> #include <mach/hardware.h> #include <mach/common.h> #include <asm/proc-fns.h> #include <asm/system.h> + #ifdef CONFIG_SMP #include <linux/smp.h> #endif #include <asm/mach-types.h> static void __iomem *wdog_base; - +extern int dvfs_core_is_active; +extern void stop_dvfs(void); /* * Reset the system. It is called by machine_restart(). */ @@ -62,6 +67,21 @@ void arch_reset(char mode, const char *cmd) return; } #endif +#ifdef CONFIG_ARCH_MX51 + /* Workaround to reset NFC_CONFIG3 register + * due to the chip warm reset does not reset it + */ + if (cpu_is_mx53()) + __raw_writel(0x20600, MX53_IO_ADDRESS(MX53_NFC_BASE_ADDR)+0x28); + if (cpu_is_mx51()) + __raw_writel(0x20600, MX51_IO_ADDRESS(MX51_NFC_BASE_ADDR)+0x28); +#endif + +#ifdef CONFIG_ARCH_MX5 + /* Stop DVFS-CORE before reboot. */ + if (dvfs_core_is_active) + stop_dvfs(); +#endif if (cpu_is_mx1()) { wcr_enable = (1 << 0); diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 306dcdd0dc38..85dcfed05c51 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -340,9 +340,9 @@ static int sdma_config_ownership(struct sdma_channel *sdmac, if (event_override && mcu_override && dsp_override) return -EINVAL; - evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR); - mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR); - dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR); + evt = readl(sdma->regs + SDMA_H_EVTOVR); + mcu = readl(sdma->regs + SDMA_H_HOSTOVR); + dsp = readl(sdma->regs + SDMA_H_DSPOVR); if (dsp_override) dsp &= ~(1 << channel); @@ -359,9 +359,9 @@ static int sdma_config_ownership(struct sdma_channel *sdmac, else mcu |= (1 << channel); - __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR); - __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR); - __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR); + writel(evt, sdma->regs + SDMA_H_EVTOVR); + writel(mcu, sdma->regs + SDMA_H_HOSTOVR); + writel(dsp, sdma->regs + SDMA_H_DSPOVR); return 0; } @@ -377,8 +377,7 @@ static int sdma_run_channel(struct sdma_channel *sdmac) init_completion(&sdmac->done); - wmb(); - __raw_writel(1 << channel, sdma->regs + SDMA_H_START); + writel(1 << channel, sdma->regs + SDMA_H_START); ret = wait_for_completion_timeout(&sdmac->done, HZ); @@ -421,9 +420,9 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) u32 val; u32 chnenbl = chnenbl_ofs(sdma, event); - val = __raw_readl(sdma->regs + chnenbl); + val = readl(sdma->regs + chnenbl); val |= (1 << channel); - __raw_writel(val, sdma->regs + chnenbl); + writel(val, sdma->regs + chnenbl); } static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) @@ -433,9 +432,9 @@ static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) u32 chnenbl = chnenbl_ofs(sdma, event); u32 val; - val = __raw_readl(sdma->regs + chnenbl); + val = readl(sdma->regs + chnenbl); val &= ~(1 << channel); - __raw_writel(val, sdma->regs + chnenbl); + writel(val, sdma->regs + chnenbl); } static void sdma_handle_channel_loop(struct sdma_channel *sdmac) @@ -512,8 +511,8 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) struct sdma_engine *sdma = dev_id; u32 stat; - stat = __raw_readl(sdma->regs + SDMA_H_INTR); - __raw_writel(stat, sdma->regs + SDMA_H_INTR); + stat = readl(sdma->regs + SDMA_H_INTR); + writel(stat, sdma->regs + SDMA_H_INTR); while (stat) { int channel = fls(stat) - 1; @@ -673,7 +672,7 @@ static void sdma_disable_channel(struct sdma_channel *sdmac) struct sdma_engine *sdma = sdmac->sdma; int channel = sdmac->channel; - __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP); + writel(1 << channel, sdma->regs + SDMA_H_STATSTOP); sdmac->status = DMA_ERROR; } @@ -778,7 +777,7 @@ static int sdma_set_channel_priority(struct sdma_channel *sdmac, return -EINVAL; } - __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); + writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); return 0; } @@ -816,8 +815,7 @@ out: static void sdma_enable_channel(struct sdma_engine *sdma, int channel) { - wmb(); - __raw_writel(1 << channel, sdma->regs + SDMA_H_START); + writel(1 << channel, sdma->regs + SDMA_H_START); } static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac) @@ -1246,7 +1244,7 @@ static int __init sdma_init(struct sdma_engine *sdma) clk_enable(sdma->clk); /* Be sure SDMA has not started yet */ - __raw_writel(0, sdma->regs + SDMA_H_C0PTR); + writel(0, sdma->regs + SDMA_H_C0PTR); sdma->channel_control = dma_alloc_coherent(NULL, MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + @@ -1269,11 +1267,11 @@ static int __init sdma_init(struct sdma_engine *sdma) /* disable all channels */ for (i = 0; i < sdma->num_events; i++) - __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i)); + writel(0, sdma->regs + chnenbl_ofs(sdma, i)); /* All channels have priority 0 */ for (i = 0; i < MAX_DMA_CHANNELS; i++) - __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); + writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); ret = sdma_request_channel(&sdma->channel[0]); if (ret) @@ -1282,16 +1280,16 @@ static int __init sdma_init(struct sdma_engine *sdma) sdma_config_ownership(&sdma->channel[0], false, true, false); /* Set Command Channel (Channel Zero) */ - __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR); + writel(0x4050, sdma->regs + SDMA_CHN0ADDR); /* Set bits of CONFIG register but with static context switching */ /* FIXME: Check whether to set ACR bit depending on clock ratios */ - __raw_writel(0, sdma->regs + SDMA_H_CONFIG); + writel(0, sdma->regs + SDMA_H_CONFIG); - __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR); + writel(ccb_phys, sdma->regs + SDMA_H_C0PTR); /* Set bits of CONFIG register with given context switching mode */ - __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); + writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); /* Initializes channel's priorities */ sdma_set_channel_priority(&sdma->channel[0], 7); diff --git a/drivers/hwmon/da9052-adc.c b/drivers/hwmon/da9052-adc.c index 6803fc2ccea3..0c3f64187da8 100755 --- a/drivers/hwmon/da9052-adc.c +++ b/drivers/hwmon/da9052-adc.c @@ -2,6 +2,7 @@ * da9052-adc.c -- ADC Driver for Dialog DA9052 * * Copyright(c) 2009 Dialog Semiconductor Ltd. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Author: Dialog Semiconductor Ltd <dchen@diasemi.com> * @@ -39,6 +40,15 @@ static const char *input_names[] = { [DA9052_ADC_VBBAT] = "BACK-UP BATTERY TEMP", }; +struct da9052 *da9052_local; + +int da9052_adc_read(unsigned char channel) +{ + if (da9052_local != NULL) + return da9052_manual_read(da9052_local, channel); + return -1; +} +EXPORT_SYMBOL(da9052_adc_read); int da9052_manual_read(struct da9052 *da9052, unsigned char channel) @@ -591,6 +601,7 @@ static int __init da9052_adc_probe(struct platform_device *pdev) /* Initialize mutex required for ADC Manual read */ mutex_init(&priv->da9052->manconv_lock); + da9052_local = priv->da9052; return 0; out_err_create2: diff --git a/drivers/hwmon/imx_ahci_hwmon.c b/drivers/hwmon/imx_ahci_hwmon.c index 073a2d1697dc..0f48f2ee7632 100644 --- a/drivers/hwmon/imx_ahci_hwmon.c +++ b/drivers/hwmon/imx_ahci_hwmon.c @@ -89,6 +89,11 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, return -1; } + /* Disable PDDQ mode when this mode is enabled */ + read_sum = readl(mmio + PORT_PHY_CTL); + if (read_sum & PORT_PHY_CTL_PDDQ_LOC) + writel(read_sum & ~PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL); + /* check rd-wr to reg */ read_sum = 0; sata_phy_cr_addr(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio); @@ -229,6 +234,10 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, a = (m2 - m1) / (m2 / 1000); temp = ((((-559) * a) / 1000) * a) / 1000 + (1379) * a / 1000 + (-458); + /* Enable PDDQ mode to save power */ + read_sum = readl(mmio + PORT_PHY_CTL); + writel(read_sum | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL); + iounmap(mmio); /* Release the clocks */ diff --git a/drivers/hwmon/mag3110.c b/drivers/hwmon/mag3110.c index 55f2114869cd..2ad56dd80c79 100755 --- a/drivers/hwmon/mag3110.c +++ b/drivers/hwmon/mag3110.c @@ -40,11 +40,12 @@ #define MAG3110_AC_OFFSET 0 #define MAG3110_DR_MODE_MASK (0x7 << 5) #define MAG3110_DR_MODE_OFFSET 5 -#define MAG3110_IRQ_USED 0 +#define MAG3110_IRQ_USED 1 -#define POLL_INTERVAL_MAX 500 -#define POLL_INTERVAL 100 -#define INT_TIMEOUT 1000 +#define POLL_INTERVAL_MIN 100 +#define POLL_INTERVAL_MAX 1000 +#define POLL_INTERVAL 500 +#define INT_TIMEOUT 1000 /* register enum for mag3110 registers */ enum { MAG3110_DR_STATUS = 0x00, @@ -83,15 +84,16 @@ struct mag3110_data { int position; }; static short MAGHAL[8][3][3] = { - { {0, 1, 0}, {-1, 0, 0}, {0, 0, 1} }, - { {1, 0, 0}, {0, 1, 0}, {0, 0, 1} }, - { {0, -1, 0}, {1, 0, 0}, {0, 0, 1} }, - { {-1, 0, 0}, {0, -1, 0}, {0, 0, 1} }, - - { {0, 1, 0}, {1, 0, 0}, {0, 0, -1} }, - { {1, 0, 0}, {0, -1, 0}, {0, 0, -1} }, - { {0, -1, 0}, {-1, 0, 0}, {0, 0, -1} }, - { {-1, 0, 0}, {0, 1, 0}, {0, 0, -1} }, + {{ 0, 1, 0}, {-1, 0, 0}, {0, 0, 1} }, + {{ 1, 0, 0}, { 0, 1, 0}, {0, 0, 1} }, + {{ 0, -1, 0}, { 1, 0, 0}, {0, 0, 1} }, + {{-1, 0, 0}, { 0, -1, 0}, {0, 0, 1} }, + + {{ 0, 1, 0}, { 1, 0, 0}, {0, 0, -1} }, + {{ 1, 0, 0}, { 0, -1, 0}, {0, 0, -1} }, + {{ 0, -1, 0}, {-1, 0, 0}, {0, 0, -1} }, + {{-1, 0, 0}, { 0, 1, 0}, {0, 0, -1} }, + }; static struct mag3110_data *mag3110_pdata; @@ -106,9 +108,11 @@ static int mag3110_adjust_position(short *x, short *y, short *z) int position = mag3110_pdata->position; if (position < 0 || position > 7) position = 0; + rawdata[0] = *x; rawdata[1] = *y; rawdata[2] = *z; + for (i = 0; i < 3; i++) { data[i] = 0; for (j = 0; j < 3; j++) @@ -142,9 +146,10 @@ static int mag3110_write_reg(struct i2c_client *client, u8 reg, char value) * This function do multiple mag3110 registers read. */ static int mag3110_read_block_data(struct i2c_client *client, u8 reg, - int count, u8 *addr) + int count, u8 *addr) { - if (i2c_smbus_read_i2c_block_data(client, reg, count, addr) < count) { + if (i2c_smbus_read_i2c_block_data + (client, reg, count, addr) < count) { dev_err(&client->dev, "i2c block read failed\n"); return -1; } @@ -172,24 +177,27 @@ static int mag3110_init_client(struct i2c_client *client) } /*************************************************************** -* -* read sensor data from mag3110 -* -***************************************************************/ + * + * read sensor data from mag3110 + * + ***************************************************************/ static int mag3110_read_data(short *x, short *y, short *z) { struct mag3110_data *data; - int retry = 3; u8 tmp_data[MAG3110_XYZ_DATA_LEN]; +#if !MAG3110_IRQ_USED + int retry = 3; int result; +#endif + if (!mag3110_pdata || mag3110_pdata->active == MAG_STANDBY) return -EINVAL; data = mag3110_pdata; #if MAG3110_IRQ_USED if (!wait_event_interruptible_timeout - (data->waitq, data->data_ready != 0, - msecs_to_jiffies(INT_TIMEOUT))) { + (data->waitq, data->data_ready != 0, + msecs_to_jiffies(INT_TIMEOUT))) { dev_dbg(&data->client->dev, "interrupt not received\n"); return -ETIME; } @@ -197,11 +205,12 @@ static int mag3110_read_data(short *x, short *y, short *z) do { msleep(1); result = i2c_smbus_read_byte_data(data->client, - MAG3110_DR_STATUS); + MAG3110_DR_STATUS); retry--; } while (!(result & MAG3110_STATUS_ZYXDR) && retry > 0); /* Clear data_ready flag after data is read out */ if (retry == 0) { + printk(KERN_DEBUG "magd wait data ready timeout....\n"); return -EINVAL; } #endif @@ -209,8 +218,7 @@ static int mag3110_read_data(short *x, short *y, short *z) data->data_ready = 0; if (mag3110_read_block_data(data->client, - MAG3110_OUT_X_MSB, MAG3110_XYZ_DATA_LEN, - tmp_data) < 0) + MAG3110_OUT_X_MSB, MAG3110_XYZ_DATA_LEN, tmp_data) < 0) return -1; *x = ((tmp_data[0] << 8) & 0xff00) | tmp_data[1]; @@ -253,7 +261,7 @@ static irqreturn_t mag3110_irq_handler(int irq, void *dev_id) } #endif static ssize_t mag3110_enable_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, char *buf) { struct i2c_client *client; int val; @@ -266,8 +274,8 @@ static ssize_t mag3110_enable_show(struct device *dev, } static ssize_t mag3110_enable_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) + struct device_attribute *attr, + const char *buf, size_t count) { struct i2c_client *client; int reg, ret, enable; @@ -277,7 +285,7 @@ static ssize_t mag3110_enable_store(struct device *dev, mutex_lock(&mag3110_lock); client = mag3110_pdata->client; reg = mag3110_read_reg(client, MAG3110_CTRL_REG1); - if (enable && mag3110_pdata->active == MAG_STANDBY) { + if (enable && mag3110_pdata->active == MAG_STANDBY) { reg |= MAG3110_AC_MASK; ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg); if (!ret) @@ -293,33 +301,33 @@ static ssize_t mag3110_enable_store(struct device *dev, msleep(100); /* Read out MSB data to clear interrupt flag automatically */ mag3110_read_block_data(client, MAG3110_OUT_X_MSB, - MAG3110_XYZ_DATA_LEN, tmp_data); + MAG3110_XYZ_DATA_LEN, tmp_data); } mutex_unlock(&mag3110_lock); return count; } static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO, - mag3110_enable_show, mag3110_enable_store); + mag3110_enable_show, mag3110_enable_store); static ssize_t mag3110_dr_mode_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, char *buf) { struct i2c_client *client; int val; client = mag3110_pdata->client; val = (mag3110_read_reg(client, MAG3110_CTRL_REG1) - & MAG3110_DR_MODE_MASK) >> MAG3110_DR_MODE_OFFSET; + & MAG3110_DR_MODE_MASK) >> MAG3110_DR_MODE_OFFSET; return sprintf(buf, "%d\n", val); } static ssize_t mag3110_dr_mode_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) + struct device_attribute *attr, + const char *buf, size_t count) { - struct i2c_client *client; + struct i2c_client *client ; int reg, ret; unsigned long val; @@ -329,7 +337,7 @@ static ssize_t mag3110_dr_mode_store(struct device *dev, client = mag3110_pdata->client; reg = mag3110_read_reg(client, MAG3110_CTRL_REG1) & - ~MAG3110_DR_MODE_MASK; + ~MAG3110_DR_MODE_MASK; reg |= (val << MAG3110_DR_MODE_OFFSET); /* MAG3110_CTRL_REG1 bit 5-7: data rate mode */ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg); @@ -340,10 +348,10 @@ static ssize_t mag3110_dr_mode_store(struct device *dev, } static DEVICE_ATTR(dr_mode, S_IWUSR | S_IRUGO, - mag3110_dr_mode_show, mag3110_dr_mode_store); + mag3110_dr_mode_show, mag3110_dr_mode_store); static ssize_t mag3110_position_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, char *buf) { int val; mutex_lock(&mag3110_lock); @@ -353,8 +361,8 @@ static ssize_t mag3110_position_show(struct device *dev, } static ssize_t mag3110_position_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) + struct device_attribute *attr, + const char *buf, size_t count) { int position; position = simple_strtoul(buf, NULL, 10); @@ -365,7 +373,7 @@ static ssize_t mag3110_position_store(struct device *dev, } static DEVICE_ATTR(position, S_IWUSR | S_IRUGO, - mag3110_position_show, mag3110_position_store); + mag3110_position_show, mag3110_position_store); static struct attribute *mag3110_attributes[] = { &dev_attr_enable.attr, @@ -379,7 +387,7 @@ static const struct attribute_group mag3110_attr_group = { }; static int __devinit mag3110_probe(struct i2c_client *client, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { struct i2c_adapter *adapter; struct input_dev *idev; @@ -388,9 +396,9 @@ static int __devinit mag3110_probe(struct i2c_client *client, adapter = to_i2c_adapter(client->dev.parent); if (!i2c_check_functionality(adapter, - I2C_FUNC_SMBUS_BYTE | - I2C_FUNC_SMBUS_BYTE_DATA | - I2C_FUNC_SMBUS_I2C_BLOCK)) + I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_I2C_BLOCK)) return -EIO; dev_info(&client->dev, "check mag3110 chip ID\n"); @@ -398,8 +406,8 @@ static int __devinit mag3110_probe(struct i2c_client *client, if (MAG3110_ID != ret) { dev_err(&client->dev, - "read chip ID 0x%x is not equal to 0x%x!\n", ret, - MAG3110_ID); + "read chip ID 0x%x is not equal to 0x%x!\n", + ret, MAG3110_ID); return -EINVAL; } data = kzalloc(sizeof(struct mag3110_data), GFP_KERNEL); @@ -426,6 +434,7 @@ static int __devinit mag3110_probe(struct i2c_client *client, } data->poll_dev->poll = mag3110_dev_poll; data->poll_dev->poll_interval = POLL_INTERVAL; + data->poll_dev->poll_interval_min = POLL_INTERVAL_MIN; data->poll_dev->poll_interval_max = POLL_INTERVAL_MAX; idev = data->poll_dev->input; idev->name = MAG3110_DRV_NAME; @@ -450,10 +459,10 @@ static int __devinit mag3110_probe(struct i2c_client *client, /* set irq type to edge rising */ #if MAG3110_IRQ_USED ret = request_irq(client->irq, mag3110_irq_handler, - IRQF_TRIGGER_RISING, client->dev.driver->name, idev); + IRQF_TRIGGER_RISING, client->dev.driver->name, idev); if (ret < 0) { dev_err(&client->dev, "failed to register irq %d!\n", - client->irq); + client->irq); goto error_rm_dev_sysfs; } #endif @@ -488,7 +497,7 @@ static int __devexit mag3110_remove(struct i2c_client *client) data->ctl_reg1 = mag3110_read_reg(client, MAG3110_CTRL_REG1); ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, - data->ctl_reg1 & ~MAG3110_AC_MASK); + data->ctl_reg1 & ~MAG3110_AC_MASK); free_irq(client->irq, data); input_unregister_polled_device(data->poll_dev); @@ -509,7 +518,7 @@ static int mag3110_suspend(struct i2c_client *client, pm_message_t mesg) if (data->active == MAG_ACTIVED) { data->ctl_reg1 = mag3110_read_reg(client, MAG3110_CTRL_REG1); ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, - data->ctl_reg1 & ~MAG3110_AC_MASK); + data->ctl_reg1 & ~MAG3110_AC_MASK); } return ret; } @@ -521,12 +530,12 @@ static int mag3110_resume(struct i2c_client *client) struct mag3110_data *data = i2c_get_clientdata(client); if (data->active == MAG_ACTIVED) { ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, - data->ctl_reg1); + data->ctl_reg1); if (data->ctl_reg1 & MAG3110_AC_MASK) { - /* Read out MSB data to clear interrupt flag automatically */ + /* Read out MSB data to clear interrupt automatically*/ mag3110_read_block_data(client, MAG3110_OUT_X_MSB, - MAG3110_XYZ_DATA_LEN, tmp_data); + MAG3110_XYZ_DATA_LEN, tmp_data); } } return ret; @@ -545,7 +554,7 @@ static const struct i2c_device_id mag3110_id[] = { MODULE_DEVICE_TABLE(i2c, mag3110_id); static struct i2c_driver mag3110_driver = { .driver = {.name = MAG3110_DRV_NAME, - .owner = THIS_MODULE,}, + .owner = THIS_MODULE,}, .suspend = mag3110_suspend, .resume = mag3110_resume, .probe = mag3110_probe, diff --git a/drivers/hwmon/mxc_mma8451.c b/drivers/hwmon/mxc_mma8451.c index 110ff3485e3f..f6469599aa95 100644 --- a/drivers/hwmon/mxc_mma8451.c +++ b/drivers/hwmon/mxc_mma8451.c @@ -33,20 +33,30 @@ #include <linux/hwmon.h> #include <linux/input-polldev.h> +#define MMA8451_DRV_NAME "mma8451" #define MMA8451_I2C_ADDR 0x1C #define MMA8451_ID 0x1A #define MMA8452_ID 0x2A #define MMA8453_ID 0x3A -#define POLL_INTERVAL_MIN 1 -#define POLL_INTERVAL_MAX 500 -#define POLL_INTERVAL 100 /* msecs */ +#define POLL_INTERVAL_MIN 20 +#define POLL_INTERVAL_MAX 1000 +#define POLL_INTERVAL 500 #define INPUT_FUZZ 32 #define INPUT_FLAT 32 #define MODE_CHANGE_DELAY_MS 100 #define MMA8451_STATUS_ZYXDR 0x08 -#define MMA8451_BUF_SIZE 7 +#define MMA8451_BUF_SIZE 6 + +#define DR_1_25MS 0 +#define DR_2_5MS 1 +#define DR_5_0MS 2 +#define DR_10_0MS 3 +#define DR_20_0MS 4 +#define DR_80_0MS 5 +#define DR_160_0MS 6 +#define DR_640_0MS 7 /* register enum for mma8451 registers */ enum { @@ -106,8 +116,8 @@ enum { }; /* The sensitivity is represented in counts/g. In 2g mode the -sensitivity is 1024 counts/g. In 4g mode the sensitivity is 512 -counts/g and in 8g mode the sensitivity is 256 counts/g. + sensitivity is 1024 counts/g. In 4g mode the sensitivity is 512 + counts/g and in 8g mode the sensitivity is 256 counts/g. */ enum { MODE_2G = 0, @@ -135,15 +145,15 @@ static struct i2c_client *mma8451_i2c_client; static int senstive_mode = MODE_2G; static int ACCHAL[8][3][3] = { - { {0, -1, 0}, {1, 0, 0}, {0, 0, 1} }, - { {-1, 0, 0}, {0, -1, 0}, {0, 0, 1} }, - { {0, 1, 0}, {-1, 0, 0}, {0, 0, 1} }, - { {1, 0, 0}, {0, 1, 0}, {0, 0, 1} }, - - { {0, -1, 0}, {-1, 0, 0}, {0, 0, -1} }, - { {-1, 0, 0}, {0, 1, 0}, {0, 0, -1} }, - { {0, 1, 0}, {1, 0, 0}, {0, 0, -1} }, - { {1, 0, 0}, {0, -1, 0}, {0, 0, -1} }, + {{ 0, -1, 0}, { 1, 0, 0}, {0, 0, 1} }, + {{-1, 0, 0}, { 0, -1, 0}, {0, 0, 1} }, + {{ 0, 1, 0}, {-1, 0, 0}, {0, 0, 1} }, + {{ 1, 0, 0}, { 0, 1, 0}, {0, 0, 1} }, + + {{ 0, -1, 0}, {-1, 0, 0}, {0, 0, -1} }, + {{-1, 0, 0}, { 0, 1, 0}, {0, 0, -1} }, + {{ 0, 1, 0}, { 1, 0, 0}, {0, 0, -1} }, + {{ 1, 0, 0}, { 0, -1, 0}, {0, 0, -1} }, }; static DEFINE_MUTEX(mma8451_lock); @@ -154,10 +164,12 @@ static int mma8451_adjust_position(short *x, short *y, short *z) int position = mma_status.position; if (position < 0 || position > 7) position = 0; + rawdata[0] = *x; rawdata[1] = *y; rawdata[2] = *z; - for (i = 0; i < 3; i++) { + + for (i = 0; i < 3 ; i++) { data[i] = 0; for (j = 0; j < 3; j++) data[i] += rawdata[j] * ACCHAL[position][i][j]; @@ -172,17 +184,23 @@ static int mma8451_change_mode(struct i2c_client *client, int mode) { int result; - mma_status.ctl_reg1 = 0; - result = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, 0); + /* Put sensor into Standby Mode by clearing the Active bit */ + mma_status.ctl_reg1 = 0x00; + result = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + mma_status.ctl_reg1); if (result < 0) goto out; + /* Write the 2g dynamic range value */ mma_status.mode = mode; result = i2c_smbus_write_byte_data(client, MMA8451_XYZ_DATA_CFG, - mma_status.mode); + mma_status.mode); if (result < 0) goto out; + + /* Set the Active bit and Data rate in CTRL Reg 1 */ mma_status.active = MMA_STANDBY; + mdelay(MODE_CHANGE_DELAY_MS); return 0; @@ -196,13 +214,15 @@ static int mma8451_read_data(short *x, short *y, short *z) u8 tmp_data[MMA8451_BUF_SIZE]; int ret; + /* Read 14-bit XYZ results using 6 byte */ ret = i2c_smbus_read_i2c_block_data(mma8451_i2c_client, - MMA8451_OUT_X_MSB, 7, tmp_data); + MMA8451_OUT_X_MSB, MMA8451_BUF_SIZE, tmp_data); if (ret < MMA8451_BUF_SIZE) { dev_err(&mma8451_i2c_client->dev, "i2c block read failed\n"); return -EIO; } + /* Concatenate the MSB and LSB */ *x = ((tmp_data[0] << 8) & 0xff00) | tmp_data[1]; *y = ((tmp_data[2] << 8) & 0xff00) | tmp_data[3]; *z = ((tmp_data[4] << 8) & 0xff00) | tmp_data[5]; @@ -213,23 +233,24 @@ static void report_abs(void) { short x, y, z; int result; - int retry = 3; mutex_lock(&mma8451_lock); if (mma_status.active == MMA_STANDBY) goto out; - /* wait for the data ready */ - do { - result = i2c_smbus_read_byte_data(mma8451_i2c_client, - MMA8451_STATUS); - retry--; - msleep(1); - } while (!(result & MMA8451_STATUS_ZYXDR) && retry > 0); - if (retry == 0) + /* Read Status register */ + result = i2c_smbus_read_byte_data(mma8451_i2c_client, MMA8451_STATUS); + + /* Check ZYXDR status bit for data available */ + if (!(result & MMA8451_STATUS_ZYXDR)) { + /* Data not ready */ goto out; + } + + /* Read XYZ data */ if (mma8451_read_data(&x, &y, &z) != 0) goto out; mma8451_adjust_position(&x, &y, &z); + /* Report XYZ data */ input_report_abs(mma8451_idev->input, ABS_X, x); input_report_abs(mma8451_idev->input, ABS_Y, y); input_report_abs(mma8451_idev->input, ABS_Z, z); @@ -244,7 +265,7 @@ static void mma8451_dev_poll(struct input_polled_dev *dev) } static ssize_t mma8451_enable_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, char *buf) { struct i2c_client *client; u8 val; @@ -262,8 +283,8 @@ static ssize_t mma8451_enable_show(struct device *dev, } static ssize_t mma8451_enable_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) + struct device_attribute *attr, + const char *buf, size_t count) { struct i2c_client *client; int ret; @@ -273,42 +294,45 @@ static ssize_t mma8451_enable_store(struct device *dev, mutex_lock(&mma8451_lock); client = mma8451_i2c_client; enable = (enable > 0) ? 1 : 0; - if (enable && mma_status.active == MMA_STANDBY) { + + if (enable && mma_status.active == MMA_STANDBY) { val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1); - ret = - i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, - val | 0x01); + /* Set the Active bit and Data rate in CTRL Reg 1 */ + val |= (DR_20_0MS<<3); + val |= 1; + ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + val); if (!ret) { mma_status.active = MMA_ACTIVED; + printk(KERN_DEBUG "mma enable setting active\n"); } - } else if (enable == 0 && mma_status.active == MMA_ACTIVED) { + } else if (enable == 0 && mma_status.active == MMA_ACTIVED) { val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1); - ret = - i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, - val & 0xFE); + ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + val & 0xFE); if (!ret) { mma_status.active = MMA_STANDBY; + printk(KERN_DEBUG "mma enable setting inactive\n"); } } mutex_unlock(&mma8451_lock); return count; } - static ssize_t mma8451_position_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, char *buf) { int position = 0; mutex_lock(&mma8451_lock); - position = mma_status.position; + position = mma_status.position ; mutex_unlock(&mma8451_lock); return sprintf(buf, "%d\n", position); } static ssize_t mma8451_position_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) + struct device_attribute *attr, + const char *buf, size_t count) { - int position; + int position; position = simple_strtoul(buf, NULL, 10); mutex_lock(&mma8451_lock); mma_status.position = position; @@ -317,9 +341,9 @@ static ssize_t mma8451_position_store(struct device *dev, } static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO, - mma8451_enable_show, mma8451_enable_store); + mma8451_enable_show, mma8451_enable_store); static DEVICE_ATTR(position, S_IWUSR | S_IRUGO, - mma8451_position_show, mma8451_position_store); + mma8451_position_show, mma8451_position_store); static struct attribute *mma8451_attributes[] = { &dev_attr_enable.attr, @@ -332,7 +356,7 @@ static const struct attribute_group mma8451_attr_group = { }; static int __devinit mma8451_probe(struct i2c_client *client, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { int result, client_id; struct input_dev *idev; @@ -341,18 +365,18 @@ static int __devinit mma8451_probe(struct i2c_client *client, mma8451_i2c_client = client; adapter = to_i2c_adapter(client->dev.parent); result = i2c_check_functionality(adapter, - I2C_FUNC_SMBUS_BYTE | - I2C_FUNC_SMBUS_BYTE_DATA); + I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA); if (!result) goto err_out; client_id = i2c_smbus_read_byte_data(client, MMA8451_WHO_AM_I); - if (client_id != MMA8451_ID && client_id != MMA8452_ID - && client_id != MMA8453_ID) { + if (client_id != MMA8451_ID && client_id != MMA8452_ID && + client_id != MMA8453_ID) { dev_err(&client->dev, - "read chip ID 0x%x is not equal to 0x%x or 0x%x!\n", - result, MMA8451_ID, MMA8452_ID); + "read chip ID 0x%x is not equal to 0x%x \ + or 0x%x!\n", result, MMA8451_ID, MMA8452_ID); result = -EINVAL; goto err_out; } @@ -361,14 +385,15 @@ static int __devinit mma8451_probe(struct i2c_client *client, result = mma8451_change_mode(client, senstive_mode); if (result) { dev_err(&client->dev, - "error when init mma8451 chip:(%d)\n", result); + "error when init mma8451 chip:(%d)\n", result); goto err_out; } hwmon_dev = hwmon_device_register(&client->dev); if (!hwmon_dev) { result = -ENOMEM; - dev_err(&client->dev, "error when register hwmon device\n"); + dev_err(&client->dev, + "error when register hwmon device\n"); goto err_out; } @@ -417,9 +442,9 @@ static int mma8451_stop_chip(struct i2c_client *client) int ret = 0; if (mma_status.active == MMA_ACTIVED) { mma_status.ctl_reg1 = i2c_smbus_read_byte_data(client, - MMA8451_CTRL_REG1); + MMA8451_CTRL_REG1); ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, - mma_status.ctl_reg1 & 0xFE); + mma_status.ctl_reg1 & 0xFE); } return ret; } @@ -447,25 +472,24 @@ static int mma8451_resume(struct device *dev) struct i2c_client *client = to_i2c_client(dev); if (mma_status.active == MMA_ACTIVED) ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, - mma_status.ctl_reg1); + mma_status.ctl_reg1); return ret; } #endif static const struct i2c_device_id mma8451_id[] = { - {"mma8451", 0}, + {MMA8451_DRV_NAME, 0}, }; - MODULE_DEVICE_TABLE(i2c, mma8451_id); static SIMPLE_DEV_PM_OPS(mma8451_pm_ops, mma8451_suspend, mma8451_resume); static struct i2c_driver mma8451_driver = { .driver = { - .name = "mma8451", - .owner = THIS_MODULE, - .pm = &mma8451_pm_ops, - }, + .name = MMA8451_DRV_NAME, + .owner = THIS_MODULE, + .pm = &mma8451_pm_ops, + }, .probe = mma8451_probe, .remove = __devexit_p(mma8451_remove), .id_table = mma8451_id, diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig index b9474aa7f043..2dcdb20e4c61 100644 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@ -335,18 +335,6 @@ config KEYBOARD_MCS To compile this driver as a module, choose M here: the module will be called mcs_touchkey. -config KEYBOARD_MPR121 - tristate "Freescale MPR121 Touchkey" - depends on I2C - help - Say Y here if you have Freescale MPR121 touchkey controller - chip in your system. - - If unsure, say N. - - To compile this driver as a module, choose M here: the - module will be called mpr121_touchkey. - config KEYBOARD_IMX tristate "IMX keypad support" depends on ARCH_MXC diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile index 6791e8b45289..1b0d7ad2814a 100644 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@ -28,7 +28,6 @@ obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o obj-$(CONFIG_KEYBOARD_MATRIX) += matrix_keypad.o obj-$(CONFIG_KEYBOARD_MAX7359) += max7359_keypad.o obj-$(CONFIG_KEYBOARD_MCS) += mcs_touchkey.o -obj-$(CONFIG_KEYBOARD_MPR121) += mpr121_touchkey.o obj-$(CONFIG_KEYBOARD_NEWTON) += newtonkbd.o obj-$(CONFIG_KEYBOARD_NOMADIK) += nomadik-ske-keypad.o obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o diff --git a/drivers/input/keyboard/mpr121.c b/drivers/input/keyboard/mpr121.c index 7aae302758c5..aa5e4e2523fd 100644 --- a/drivers/input/keyboard/mpr121.c +++ b/drivers/input/keyboard/mpr121.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -30,7 +30,6 @@ #include <linux/delay.h> #include <linux/bitops.h> - struct mpr121_touchkey_data { struct i2c_client *client; struct input_dev *input_dev; @@ -88,8 +87,7 @@ static irqreturn_t mpr_touchkey_interrupt(int irq, void *dev_id) data->statusbits = reg; data->key_val = data->keycodes[key_num]; - input_event(input, EV_MSC, MSC_SCAN, data->key_val); - input_report_key(input, data->key_val, pressed); + input_event(input, EV_KEY, data->key_val, !!pressed); input_sync(input); dev_dbg(&client->dev, "key %d %d %s\n", key_num, data->key_val, @@ -125,6 +123,7 @@ static int mpr121_phys_init(struct mpr121_platform_data *pdata, if (ret < 0) goto err_i2c_write; } + /* setup auto-register by vdd,the formula please ref:AN3889 */ vdd = pdata->vdd_uv / 1000; usl = ((vdd - 700) * 256) / vdd; @@ -140,7 +139,7 @@ static int mpr121_phys_init(struct mpr121_platform_data *pdata, if (ret < 0) goto err_i2c_write; ret = i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR, - data->keycount); + ECR_CL_BT_5BIT_VAL | (data->keycount & 0xf)); if (ret < 0) goto err_i2c_write; @@ -203,11 +202,10 @@ static int __devinit mpr_touchkey_probe(struct i2c_client *client, input_dev->keycodemax = data->keycount; for (i = 0; i < input_dev->keycodemax; i++) { - __set_bit(pdata->matrix[i], input_dev->keybit); + input_set_capability(input_dev, EV_KEY, pdata->matrix[i]); data->keycodes[i] = pdata->matrix[i]; } - input_set_capability(input_dev, EV_MSC, MSC_SCAN); input_set_drvdata(input_dev, data); error = request_threaded_irq(client->irq, NULL, @@ -264,7 +262,8 @@ static int mpr_resume(struct i2c_client *client) if (device_may_wakeup(&client->dev)) disable_irq_wake(client->irq); - i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR, data->keycount); + i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR, + ECR_CL_BT_5BIT_VAL | (data->keycount & 0xf)); return 0; } diff --git a/drivers/input/misc/da9052_onkey.c b/drivers/input/misc/da9052_onkey.c index 2271b59261fa..5d223b62e973 100644 --- a/drivers/input/misc/da9052_onkey.c +++ b/drivers/input/misc/da9052_onkey.c @@ -1,3 +1,15 @@ +/* + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * da9052_onkey.c: Onkey driver for DA9052 + */ + #include <linux/module.h> #include <linux/init.h> #include <linux/input.h> @@ -14,6 +26,9 @@ struct da9052_onkey_data { struct input_dev *input; }; +/* Flag to enable key events during suspend */ +static bool enable_onkey_events; + static void da9052_onkey_report_event(struct da9052_eh_nb *eh_data, unsigned int event) { @@ -33,9 +48,12 @@ static void da9052_onkey_report_event(struct da9052_eh_nb *eh_data, da9052_unlock(da9052_onkey->da9052); msg.data = msg.data & DA9052_EVENTB_ENONKEY; - input_report_key(da9052_onkey->input, KEY_POWER, msg.data); - input_sync(da9052_onkey->input); - printk(KERN_INFO "DA9052 ONKEY EVENT REPORTED \n"); + /* We need onkey events only in suspend mode */ + if (enable_onkey_events) { + input_report_key(da9052_onkey->input, KEY_POWER, msg.data); + input_sync(da9052_onkey->input); + } + pr_debug("DA9052 ONKEY EVENT REPORTED\n"); } static int __devinit da9052_onkey_probe(struct platform_device *pdev) @@ -105,12 +123,34 @@ static int __devexit da9052_onkey_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int da9052_onkey_suspend(struct device *dev) +{ + enable_onkey_events = true; + return 0; +} + +static int da9052_onkey_resume(struct device *dev) +{ + enable_onkey_events = false; + return 0; +} + +static const struct dev_pm_ops da9052_onkey_pm_ops = { + .suspend = da9052_onkey_suspend, + .resume = da9052_onkey_resume, +}; +#else +static const struct dev_pm_ops da9052_onkey_pm_ops = {}; +#endif + static struct platform_driver da9052_onkey_driver = { .probe = da9052_onkey_probe, .remove = __devexit_p(da9052_onkey_remove), .driver = { .name = "da9052-onkey", .owner = THIS_MODULE, + .pm = &da9052_onkey_pm_ops, } }; diff --git a/drivers/input/touchscreen/p1003_ts.c b/drivers/input/touchscreen/p1003_ts.c index 39e9c6573727..40be64909f7c 100644 --- a/drivers/input/touchscreen/p1003_ts.c +++ b/drivers/input/touchscreen/p1003_ts.c @@ -301,7 +301,7 @@ static int __devinit p1003_probe(struct i2c_client *client, goto err_free_wq; /* set irq type to edge falling */ - set_irq_type(p1003->irq, IRQF_TRIGGER_FALLING); + irq_set_irq_type(p1003->irq, IRQF_TRIGGER_FALLING); ret = request_irq(p1003->irq, p1003_irq, 0, client->dev.driver->name, p1003); if (ret < 0) { diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c index 8b4a658ceb50..a96955e8bea7 100755 --- a/drivers/mfd/da9052-core.c +++ b/drivers/mfd/da9052-core.c @@ -2,7 +2,7 @@ * da9052-core.c -- Device access for Dialog DA9052 * * Copyright(c) 2009 Dialog Semiconductor Ltd. - * + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Author: Dialog Semiconductor Ltd <dchen@diasemi.com> * * This program is free software; you can redistribute it and/or modify it @@ -34,6 +34,7 @@ struct da9052_eh_nb eve_nb_array[EVE_CNT]; static struct da9052_ssc_ops ssc_ops; struct mutex manconv_lock; static struct semaphore eve_nb_array_lock; +static struct da9052 *da9052_data; void da9052_lock(struct da9052 *da9052) { @@ -248,17 +249,16 @@ static int process_events(struct da9052 *da9052, int events_sts) /* Check if interrupt is received for this event */ if (!((tmp_events_sts >> cnt) & 0x1)) /* Event bit is not set for this event */ - /* Move to next event */ + /* Move to next priority event */ continue; if (event == PEN_DOWN_EVE) { if (list_empty(&(eve_nb_array[event].nb_list))) continue; } - /* Event bit is set, execute all registered call backs */ if (down_interruptible(&eve_nb_array_lock)){ - printk(KERN_CRIT "Can't acquire eve_nb_array_lock \n"); + printk(KERN_CRIT "Can't acquire eve_nb_array_lock\n"); return -EIO; } @@ -281,14 +281,11 @@ void eh_workqueue_isr(struct work_struct *work) container_of(work, struct da9052, eh_isr_work); struct da9052_ssc_msg eve_data[4]; - struct da9052_ssc_msg eve_mask_data[4]; int events_sts, ret; - u32 mask; unsigned char cnt = 0; /* nIRQ is asserted, read event registeres to know what happened */ events_sts = 0; - mask = 0; /* Prepare ssc message to read all four event registers */ for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++) { @@ -296,13 +293,7 @@ void eh_workqueue_isr(struct work_struct *work) eve_data[cnt].data = 0; } - /* Prepare ssc message to read all four event registers */ - for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++) { - eve_mask_data[cnt].addr = (DA9052_IRQMASKA_REG + cnt); - eve_mask_data[cnt].data = 0; - } - - /* Now read all event and mask registers */ + /* Now read all event registers */ da9052_lock(da9052); ret = da9052_ssc_read_many(da9052,eve_data, DA9052_EVE_REGISTERS); @@ -312,22 +303,10 @@ void eh_workqueue_isr(struct work_struct *work) return; } - ret = da9052_ssc_read_many(da9052,eve_mask_data, DA9052_EVE_REGISTERS); - if (ret) { - enable_irq(da9052->irq); - da9052_unlock(da9052); - return; - } /* Collect all events */ for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++) - events_sts |= (eve_data[cnt].data << (DA9052_EVE_REGISTER_SIZE - * cnt)); - /* Collect all mask */ - for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++) - mask |= (eve_mask_data[cnt].data << (DA9052_EVE_REGISTER_SIZE - * cnt)); - events_sts &= ~mask; - da9052_unlock(da9052); + events_sts |= ((eve_data[cnt].data&0xff) << + (DA9052_EVE_REGISTER_SIZE * cnt)); /* Check if we really got any event */ if (events_sts == 0) { @@ -335,6 +314,7 @@ void eh_workqueue_isr(struct work_struct *work) da9052_unlock(da9052); return; } + da9052_unlock(da9052); /* Process all events occurred */ process_events(da9052, events_sts); @@ -376,7 +356,7 @@ static int da9052_add_subdevice_pdata(struct da9052 *da9052, struct mfd_cell cell = { .name = name, .platform_data = pdata, - .data_size = pdata_size, + .pdata_size = pdata_size, }; return mfd_add_devices(da9052->dev, -1, &cell, 1, NULL, 0); } @@ -399,6 +379,7 @@ static int add_da9052_devices(struct da9052 *da9052) }; struct da9052_tsi_platform_data tsi_data = *(pdata->tsi_data); + struct da9052_bat_platform_data bat_data = *(pdata->bat_data); if (pdata && pdata->init) { ret = pdata->init(da9052); @@ -406,7 +387,6 @@ static int add_da9052_devices(struct da9052 *da9052) return ret; } else pr_err("No platform initialisation supplied\n"); - ret = da9052_add_subdevice(da9052, "da9052-rtc"); if (ret) return ret; @@ -449,7 +429,8 @@ static int add_da9052_devices(struct da9052 *da9052) if (ret) return ret; - ret = da9052_add_subdevice(da9052, "da9052-bat"); + ret = da9052_add_subdevice_pdata(da9052, "da9052-bat", + &bat_data, sizeof(bat_data)); if (ret) return ret; @@ -493,6 +474,7 @@ int da9052_ssc_init(struct da9052 *da9052) ssc_ops.read_many = da9052_i2c_read_many; } else return -1; + /* Assign the EH notifier block register/de-register functions */ da9052->register_event_notifier = eh_register_nb; da9052->unregister_event_notifier = eh_unregister_nb; @@ -504,16 +486,34 @@ int da9052_ssc_init(struct da9052 *da9052) add_da9052_devices(da9052); INIT_WORK(&da9052->eh_isr_work, eh_workqueue_isr); + ssc_msg.addr = DA9052_IRQMASKA_REG; ssc_msg.data = 0xff; da9052->write(da9052, &ssc_msg); ssc_msg.addr = DA9052_IRQMASKC_REG; ssc_msg.data = 0xff; da9052->write(da9052, &ssc_msg); + + /* read chip version */ + ssc_msg.addr = DA9052_CHIPID_REG; + da9052->read(da9052, &ssc_msg); + pr_info("DA9053 chip ID reg read=0x%x ", ssc_msg.data); + if ((ssc_msg.data & DA9052_CHIPID_MRC) == 0x80) { + da9052->chip_version = DA9053_VERSION_AA; + pr_info("AA version probed\n"); + } else if ((ssc_msg.data & DA9052_CHIPID_MRC) == 0xa0) { + da9052->chip_version = DA9053_VERSION_BB; + pr_info("BB version probed\n"); + } else { + da9052->chip_version = 0; + pr_info("unknown chip version\n"); + } + if (request_irq(da9052->irq, da9052_eh_isr, IRQ_TYPE_LEVEL_LOW, DA9052_EH_DEVICE_NAME, da9052)) return -EIO; enable_irq_wake(da9052->irq); + da9052_data = da9052; return 0; } @@ -530,6 +530,27 @@ void da9052_ssc_exit(struct da9052 *da9052) return; } +void da9053_power_off(void) +{ + struct da9052_ssc_msg ssc_msg; + struct da9052_ssc_msg ssc_msg_dummy[2]; + if (!da9052_data) + return; + + ssc_msg.addr = DA9052_CONTROLB_REG; + da9052_data->read(da9052_data, &ssc_msg); + ssc_msg_dummy[0].addr = DA9052_CONTROLB_REG; + ssc_msg_dummy[0].data = ssc_msg.data | DA9052_CONTROLB_SHUTDOWN; + ssc_msg_dummy[1].addr = DA9052_GPID9_REG; + ssc_msg_dummy[1].data = 0; + da9052_data->write_many(da9052_data, &ssc_msg_dummy[0], 2); +} + +int da9053_get_chip_version(void) +{ + return da9052_data->chip_version; +} + MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>"); MODULE_DESCRIPTION("DA9052 MFD Core"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c index 4f050896d962..214f657866ee 100755 --- a/drivers/mfd/da9052-i2c.c +++ b/drivers/mfd/da9052-i2c.c @@ -1,5 +1,6 @@ /* * Copyright(c) 2009 Dialog Semiconductor Ltd. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,23 +22,21 @@ static struct da9052 *da9052_i2c; static int da9052_i2c_is_connected(void) { + struct da9052_ssc_msg msg; + int retries = 10, ret = -1; + + msg.addr = DA9052_INTERFACE_REG; + do { + /* Test i2c connectivity by reading the GPIO_0-1 register */ + if (0 != da9052_i2c_read(da9052_i2c, &msg)) { + printk(KERN_INFO"da9052_i2c_is_connected - i2c read failed.....\n"); + } else { + printk(KERN_INFO"da9052_i2c_is_connected - i2c read success....\n"); + ret = 0; + } + } while (ret != 0 && retries--); - struct da9052_ssc_msg msg; - - //printk("Entered da9052_i2c_is_connected.............\n"); - - msg.addr = DA9052_INTERFACE_REG; - - /* Test spi connectivity by performing read of the GPIO_0-1 register */ - if ( 0 != da9052_i2c_read(da9052_i2c, &msg)) { - printk("da9052_i2c_is_connected - i2c read failed.............\n"); - return -1; - } - else { - printk("da9052_i2c_is_connected - i2c read success..............\n"); - return 0; - } - + return ret; } static int __devinit da9052_i2c_probe(struct i2c_client *client, diff --git a/drivers/mfd/mc-pmic-core.c b/drivers/mfd/mc-pmic-core.c index db46ef1da050..001a34d34cab 100644 --- a/drivers/mfd/mc-pmic-core.c +++ b/drivers/mfd/mc-pmic-core.c @@ -505,7 +505,6 @@ mc_pmic_add_subdevice_pdata(struct mc_pmic *mc_pmic, struct mfd_cell cell = { .platform_data = pdata, - .data_size = pdata_size, }; /* there is no asnprintf in the kernel :-( */ @@ -556,7 +555,6 @@ mc_pmic_probe(struct i2c_client *client, const struct i2c_device_id *id) if (ret) { err_mask: - err_revision: mc_pmic_unlock(mc_pmic); dev_set_drvdata(&client->dev, NULL); kfree(mc_pmic); diff --git a/drivers/misc/pmem.c b/drivers/misc/pmem.c index 3027618a6a9f..a5363b99ecfb 100644 --- a/drivers/misc/pmem.c +++ b/drivers/misc/pmem.c @@ -34,6 +34,7 @@ #define PMEM_MIN_ALLOC PAGE_SIZE #define PMEM_DEBUG 1 +#define PMEM_VADDR_SUPPORT /* indicates that a refernce to this file has been taken via get_pmem_file, * the file should not be released until put_pmem_file is called */ @@ -1307,8 +1308,10 @@ int pmem_setup(struct android_pmem_platform_data *pdata, &debug_fops); #endif return 0; +#ifdef PMEM_VADDR_SUPPORT error_cant_remap: kfree(pmem[id].bitmap); +#endif err_no_mem_for_metadata: misc_deregister(&pmem[id].dev); err_cant_register_device: diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 74c2eb063f1f..465938e7ba2f 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -32,6 +32,7 @@ #define SDHCI_VENDOR_SPEC 0xC0 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 +#define SDHCI_MIX_CTRL_AC12EN (1 << 2) #define SDHCI_MIX_CTRL_AC23EN (1 << 7) #define SDHCI_MIX_CTRL_EXE_TUNE (1 << 22) #define SDHCI_MIX_CTRL_SMPCLK_SEL (1 << 23) @@ -433,9 +434,12 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) } imx_data->scratchpad = val; - if (val & SDHCI_TRNS_AUTO_CMD23) + if (cpu_is_mx6() && (val & SDHCI_TRNS_AUTO_CMD23)) imx_data->scratchpad |= SDHCI_MIX_CTRL_AC23EN; + if (val & SDHCI_TRNS_AUTO_CMD12) + imx_data->scratchpad |= SDHCI_MIX_CTRL_AC12EN; + return; case SDHCI_COMMAND: if ((host->cmd->opcode == MMC_STOP_TRANSMISSION) @@ -702,7 +706,12 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd | SDHCI_QUIRK_BROKEN_ADMA; if (cpu_is_mx6()) - host->quirks2 |= SDHCI_QUIRK_BROKEN_AUTO_CMD23, + host->quirks2 |= SDHCI_QUIRK_BROKEN_AUTO_CMD23; + + if(cpu_is_mx53()) { + host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; + host->quirks2 |= SDHCI_QUIRK_BROKEN_AUTO_CMD23; + } /* write_protect can't be routed to controller, use gpio */ sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 1aedbe436c25..094e9463b073 100755 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2645,7 +2645,7 @@ int sdhci_add_host(struct sdhci_host *host) } else mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; - mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; + mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE; if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) host->flags |= SDHCI_AUTO_CMD12; @@ -2656,6 +2656,7 @@ int sdhci_add_host(struct sdhci_host *host) ((host->flags & SDHCI_USE_ADMA) || !(host->flags & SDHCI_USE_SDMA))) { host->flags |= SDHCI_AUTO_CMD23; + mmc->caps |= MMC_CAP_CMD23; DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); } else { DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); diff --git a/drivers/mxc/amd-gpu/common/gsl_memmgr.c b/drivers/mxc/amd-gpu/common/gsl_memmgr.c index 75f250ae59b1..3248f6d46554 100644 --- a/drivers/mxc/amd-gpu/common/gsl_memmgr.c +++ b/drivers/mxc/amd-gpu/common/gsl_memmgr.c @@ -479,6 +479,8 @@ kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_m unsigned int blksize; unsigned int baseaddr, alignedbaseaddr, alignfragment; int freeblk, alignmentshift; + memblk_t *ptrbest = NULL; + unsigned int fitsize = ~0UL; kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_memarena_alloc(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x, int size=%d, gsl_memdesc_t *memdesc=%M)\n", memarena, flags, size, memdesc ); @@ -542,17 +544,33 @@ kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_m do { + int aba; // align base address - baseaddr = ptrfree->blkaddr + memarena->gpubaseaddr; - alignedbaseaddr = gsl_memarena_alignaddr(baseaddr, alignmentshift); + baseaddr = ptrfree->blkaddr + memarena->gpubaseaddr; + aba = gsl_memarena_alignaddr(baseaddr, alignmentshift); - alignfragment = alignedbaseaddr - baseaddr; - - if (ptrfree->blksize >= blksize + alignfragment) - { - result = GSL_SUCCESS; - freeblk = 1; - + if (aba - baseaddr == 0 && ptrfree->blksize == blksize) { + ptrbest = ptrfree; + alignfragment = aba - baseaddr; + alignedbaseaddr = aba; + result = GSL_SUCCESS; + break; + } + + if ((ptrfree->blksize >= blksize + aba - baseaddr) && + (fitsize > ptrfree->blksize)) { + fitsize = ptrfree->blksize; + alignfragment = aba - baseaddr; + alignedbaseaddr = aba; + result = GSL_SUCCESS; + ptrbest = ptrfree; + } + + ptrfree = ptrfree->next; + + } while (ptrfree != memarena->freelist.allocrover); + + if (ptrbest) { memdesc->gpuaddr = alignedbaseaddr; memdesc->hostptr = kgsl_memarena_gethostptr(memarena, memdesc->gpuaddr); memdesc->size = blksize; @@ -561,50 +579,41 @@ kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_m { // insert new node to handle newly created (small) fragment p = kgsl_memarena_getmemblknode(memarena); - p->blkaddr = ptrfree->blkaddr; + p->blkaddr = ptrbest->blkaddr; p->blksize = alignfragment; - p->next = ptrfree; - p->prev = ptrfree->prev; - ptrfree->prev->next = p; - ptrfree->prev = p; + p->next = ptrbest; + p->prev = ptrbest->prev; + ptrbest->prev->next = p; + ptrbest->prev = p; - if (ptrfree == memarena->freelist.head) - { - memarena->freelist.head = p; - } + if (ptrbest == memarena->freelist.head) + memarena->freelist.head = p; } - ptrfree->blkaddr += alignfragment + blksize; - ptrfree->blksize -= alignfragment + blksize; + ptrbest->blkaddr += alignfragment + blksize; + ptrbest->blksize -= alignfragment + blksize; - memarena->freelist.allocrover = ptrfree; + memarena->freelist.allocrover = ptrbest; - if (ptrfree->blksize == 0 && ptrfree != ptrlast) - { - ptrfree->prev->next = ptrfree->next; - ptrfree->next->prev = ptrfree->prev; - if (ptrfree == memarena->freelist.head) - { - memarena->freelist.head = ptrfree->next; - } - if (ptrfree == memarena->freelist.allocrover) - { - memarena->freelist.allocrover = ptrfree->next; - } - if (ptrfree == memarena->freelist.freerover) - { - memarena->freelist.freerover = ptrfree->prev; - } - p = ptrfree; - ptrfree = ptrfree->prev; - kgsl_memarena_releasememblknode(memarena, p); - } - } + if (ptrbest->blksize == 0 && ptrbest != ptrlast) { + ptrbest->prev->next = ptrbest->next; + ptrbest->next->prev = ptrbest->prev; - ptrfree = ptrfree->next; + if (ptrbest == memarena->freelist.head) + memarena->freelist.head = ptrbest->next; + + if (ptrbest == memarena->freelist.allocrover) + memarena->freelist.allocrover = ptrbest->next; + + if (ptrbest == memarena->freelist.freerover) + memarena->freelist.freerover = ptrbest->prev; - } while (!freeblk && ptrfree != memarena->freelist.allocrover); + p = ptrbest; + ptrbest = ptrbest->prev; + kgsl_memarena_releasememblknode(memarena, p); + } + } GSL_MEMARENA_UNLOCK(); diff --git a/drivers/mxc/amd-gpu/common/gsl_mmu.c b/drivers/mxc/amd-gpu/common/gsl_mmu.c index 810a058a515d..8259896775b6 100644 --- a/drivers/mxc/amd-gpu/common/gsl_mmu.c +++ b/drivers/mxc/amd-gpu/common/gsl_mmu.c @@ -89,7 +89,8 @@ const unsigned int GSL_PT_PAGE_AP[4] = {(GSL_PT_PAGE_READ | GSL_PT_PAGE_WRITE), #define GSL_PT_MAP_SETBITS(pte, bits) (GSL_PT_MAP_GET(pte) |= (((unsigned int) bits) & GSL_PT_PAGE_AP_MASK)) #define GSL_PT_MAP_SETADDR(pte, pageaddr) (GSL_PT_MAP_GET(pte) = (GSL_PT_MAP_GET(pte) & ~GSL_PT_PAGE_ADDR_MASK) | (((unsigned int) pageaddr) & GSL_PT_PAGE_ADDR_MASK)) -#define GSL_PT_MAP_RESET(pte) (GSL_PT_MAP_GET(pte) = 0) +/* reserve RV and WV bits to work around READ_PROTECTION_ERROR in some cases */ +#define GSL_PT_MAP_RESET(pte) (GSL_PT_MAP_GET(pte) &= ~GSL_PT_PAGE_ADDR_MASK) #define GSL_PT_MAP_RESETBITS(pte, bits) (GSL_PT_MAP_GET(pte) &= ~(((unsigned int) bits) & GSL_PT_PAGE_AP_MASK)) #define GSL_MMU_VIRT_TO_PAGE(va) *((unsigned int *)(pagetable->base.gpuaddr + (GSL_PT_ENTRY_GET(va) * GSL_PT_ENTRY_SIZEBYTES))) @@ -708,6 +709,16 @@ kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *sca //---------------------------------------------------------------------------- +static bool is_superpte_empty(gsl_pagetable_t *pagetable, unsigned int superpte) +{ + int i; + for (i = 0; i < GSL_PT_SUPER_PTE; i++) { + if (GSL_PT_MAP_GET(superpte+i)) + return false; + } + return true; +} + int kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid) { @@ -777,7 +788,10 @@ kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pi { do { - pagetable->last_superpte -= GSL_PT_SUPER_PTE; + if (is_superpte_empty(pagetable, superpte)) + pagetable->last_superpte -= GSL_PT_SUPER_PTE; + else + break; } while (!GSL_PT_MAP_GETADDR(pagetable->last_superpte) && pagetable->last_superpte >= GSL_PT_SUPER_PTE); } diff --git a/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c index fb05ff3cbe14..112fd086cf81 100644 --- a/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c +++ b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c @@ -342,8 +342,6 @@ kgsl_ringbuffer_checkpm4(unsigned int* cmds, unsigned int sizedwords, int pmodeo static void kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb) { - unsigned int value; - kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "--> static void kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl index 03f6f4cd35e4..058548b41522 100644 --- a/drivers/mxc/amd-gpu/common/pm4_microcode.inl +++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. +/* Copyright (c) 2008-2011, QUALCOMM Incorporated. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -26,12 +26,14 @@ * */ +// Microcode Source Version 20111020.a + #ifndef PM4_MICROCODE_H #define PM4_MICROCODE_H -#define PM4_MICROCODE_VERSION 300684 +#define PM4_MICROCODE_VERSION 422468 -#define PM4_MICROCODE_SIZE 768 +#define PM4_MICROCODE_SIZE 768 // Size of PM4 microcode in QWORD #ifdef _PRIMLIB_INCLUDE @@ -47,20 +49,20 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0xd9004800, 0x000 }, { 0x00000000, 0x00400000, 0x000 }, { 0x00000000, 0x34e00000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0x00600000, 0x287 }, { 0x0000ffff, 0xc0280a20, 0x000 }, { 0x00000000, 0x00294582, 0x000 }, { 0x00000000, 0xd9004800, 0x000 }, { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0x00600000, 0x287 }, { 0x0000ffff, 0xc0284620, 0x000 }, { 0x00000000, 0xd9004800, 0x000 }, { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a8 }, + { 0x00000000, 0x00600000, 0x2ac }, { 0x00000000, 0xc0200c00, 0x000 }, { 0x000021fc, 0x0029462c, 0x000 }, { 0x00000000, 0x00404803, 0x021 }, - { 0x00000000, 0x00600000, 0x2a8 }, + { 0x00000000, 0x00600000, 0x2ac }, { 0x00000000, 0xc0200000, 0x000 }, { 0x00000000, 0xc0200c00, 0x000 }, { 0x000021fc, 0x0029462c, 0x000 }, @@ -78,7 +80,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x0000000e, 0x00404811, 0x000 }, { 0x00000394, 0x00204411, 0x000 }, { 0x00000001, 0xc0404811, 0x000 }, - { 0x00000000, 0x00600000, 0x2a8 }, + { 0x00000000, 0x00600000, 0x2ac }, { 0x000021f9, 0x0029462c, 0x000 }, { 0x00000008, 0xc0210a20, 0x000 }, { 0x00000000, 0x14e00000, 0x02d }, @@ -88,53 +90,48 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x0000001b, 0x002f0222, 0x000 }, { 0x00000000, 0x0ce00000, 0x043 }, { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04a }, + { 0x00000000, 0x0ce00000, 0x045 }, { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x051 }, + { 0x00000000, 0x0ce00000, 0x047 }, { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x058 }, + { 0x00000000, 0x0ce00000, 0x049 }, { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x058 }, + { 0x00000000, 0x0ce00000, 0x049 }, { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x060 }, + { 0x00000000, 0x0ce00000, 0x05b }, { 0x000021f9, 0x0029462c, 0x000 }, { 0x00000000, 0xc0404802, 0x000 }, { 0x0000001f, 0x40280a20, 0x000 }, { 0x0000001b, 0x002f0222, 0x000 }, { 0x00000000, 0x0ce00000, 0x043 }, { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04a }, - { 0x00000000, 0x00400000, 0x051 }, + { 0x00000000, 0x0ce00000, 0x045 }, + { 0x00000000, 0x00400000, 0x047 }, { 0x0000001f, 0xc0210e20, 0x000 }, - { 0x00000612, 0x00204411, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x000021f9, 0x0029462c, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, + { 0x00000612, 0x00404411, 0x04c }, { 0x0000001e, 0xc0210e20, 0x000 }, - { 0x00000600, 0x00204411, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x000021f9, 0x0029462c, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, + { 0x00000600, 0x00404411, 0x04c }, { 0x0000001e, 0xc0210e20, 0x000 }, - { 0x00000605, 0x00204411, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x000021f9, 0x0029462c, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, + { 0x00000605, 0x00404411, 0x04c }, { 0x0000001f, 0x40280a20, 0x000 }, { 0x0000001f, 0xc0210e20, 0x000 }, { 0x0000060a, 0x00204411, 0x000 }, { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000080, 0x00201c11, 0x000 }, { 0x000021f9, 0x0029462c, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000001f, 0xc0680a20, 0x2a8 }, + { 0x00000000, 0x00204802, 0x000 }, + { 0x00000000, 0x00600000, 0x130 }, + { 0x00000000, 0x002f0070, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, + { 0x00000001, 0x00331e27, 0x000 }, + { 0x00000000, 0x002f0227, 0x000 }, + { 0x00000000, 0x0ae00000, 0x054 }, + { 0x00000000, 0x00400000, 0x051 }, + { 0x0000001f, 0xc0680a20, 0x2ac }, { 0x000021f9, 0x0029462c, 0x000 }, { 0x00000000, 0x00404802, 0x000 }, { 0x8100ffff, 0x00204411, 0x000 }, @@ -142,24 +139,24 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00001fff, 0x40280a20, 0x000 }, { 0x80000000, 0x40280e20, 0x000 }, { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x2b2 }, + { 0x00040000, 0x00694622, 0x2b4 }, { 0x00000000, 0x00201410, 0x000 }, { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x06d }, - { 0x00000000, 0xc0401800, 0x070 }, + { 0x00000000, 0x0ae00000, 0x068 }, + { 0x00000000, 0xc0401800, 0x06b }, { 0x00001fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x2b2 }, + { 0x00040000, 0x00694626, 0x2b4 }, { 0x00000000, 0x00201810, 0x000 }, { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ae00000, 0x073 }, - { 0x00000000, 0xc0401c00, 0x076 }, + { 0x00000000, 0x0ae00000, 0x06e }, + { 0x00000000, 0xc0401c00, 0x071 }, { 0x00001fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x2b2 }, + { 0x00040000, 0x00694627, 0x2b4 }, { 0x00000000, 0x00201c10, 0x000 }, { 0x00000000, 0x00204402, 0x000 }, { 0x00000000, 0x002820c5, 0x000 }, { 0x00000000, 0x004948e8, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0x00600000, 0x287 }, { 0x00000010, 0x40210a20, 0x000 }, { 0x000000ff, 0x00280a22, 0x000 }, { 0x000007ff, 0x40280e20, 0x000 }, @@ -167,25 +164,25 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000005, 0xc0211220, 0x000 }, { 0x00080000, 0x00281224, 0x000 }, { 0x00000013, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x084 }, + { 0x00000000, 0x14c00000, 0x07f }, { 0xa100ffff, 0x00204411, 0x000 }, { 0x00000000, 0x00204811, 0x000 }, { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x088 }, + { 0x00000000, 0x0ae00000, 0x083 }, { 0x00000000, 0x0020162d, 0x000 }, - { 0x00004000, 0x00500e23, 0x097 }, + { 0x00004000, 0x00500e23, 0x092 }, { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x08c }, + { 0x00000000, 0x0ae00000, 0x087 }, { 0x00000001, 0x0020162d, 0x000 }, - { 0x00004800, 0x00500e23, 0x097 }, + { 0x00004800, 0x00500e23, 0x092 }, { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x090 }, + { 0x00000000, 0x0ae00000, 0x08b }, { 0x00000003, 0x0020162d, 0x000 }, - { 0x00004900, 0x00500e23, 0x097 }, + { 0x00004900, 0x00500e23, 0x092 }, { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x094 }, + { 0x00000000, 0x0ae00000, 0x08f }, { 0x00000002, 0x0020162d, 0x000 }, - { 0x00004908, 0x00500e23, 0x097 }, + { 0x00004908, 0x00500e23, 0x092 }, { 0x00000012, 0x0020162d, 0x000 }, { 0x00002000, 0x00300e23, 0x000 }, { 0x00000000, 0x00290d83, 0x000 }, @@ -200,7 +197,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x002948e5, 0x000 }, { 0x9300ffff, 0x00204411, 0x000 }, { 0x00000000, 0x00404806, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0x00600000, 0x287 }, { 0x00000000, 0xc0200800, 0x000 }, { 0x00000000, 0xc0201400, 0x000 }, { 0x0000001f, 0x00211a25, 0x000 }, @@ -209,31 +206,31 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000010, 0x00211225, 0x000 }, { 0x8300ffff, 0x00204411, 0x000 }, { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0ae }, + { 0x00000000, 0x0ae00000, 0x0a9 }, { 0x00000000, 0x00203622, 0x000 }, - { 0x00004000, 0x00504a23, 0x0bd }, + { 0x00004000, 0x00504a23, 0x0b8 }, { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b2 }, + { 0x00000000, 0x0ae00000, 0x0ad }, { 0x00000001, 0x00203622, 0x000 }, - { 0x00004800, 0x00504a23, 0x0bd }, + { 0x00004800, 0x00504a23, 0x0b8 }, { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b6 }, + { 0x00000000, 0x0ae00000, 0x0b1 }, { 0x00000003, 0x00203622, 0x000 }, - { 0x00004900, 0x00504a23, 0x0bd }, + { 0x00004900, 0x00504a23, 0x0b8 }, { 0x00000003, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0ba }, + { 0x00000000, 0x0ae00000, 0x0b5 }, { 0x00000002, 0x00203622, 0x000 }, - { 0x00004908, 0x00504a23, 0x0bd }, + { 0x00004908, 0x00504a23, 0x0b8 }, { 0x00000012, 0x00203622, 0x000 }, { 0x00000000, 0x00290d83, 0x000 }, { 0x00002000, 0x00304a23, 0x000 }, { 0x8400ffff, 0x00204411, 0x000 }, { 0x00000000, 0xc0204800, 0x000 }, { 0x00000000, 0x21000000, 0x000 }, - { 0x00000000, 0x00400000, 0x0a4 }, + { 0x00000000, 0x00400000, 0x09f }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000001, 0x00204811, 0x000 }, - { 0x00040578, 0x00604411, 0x2b2 }, + { 0x00040578, 0x00604411, 0x2b4 }, { 0x00000000, 0xc0400000, 0x000 }, { 0x00000000, 0xc0200c00, 0x000 }, { 0x00000000, 0xc0201000, 0x000 }, @@ -241,62 +238,62 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0xc0201800, 0x000 }, { 0x00007f00, 0x00280a21, 0x000 }, { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0cd }, + { 0x00000000, 0x0ce00000, 0x0c8 }, { 0x00000000, 0xc0201c00, 0x000 }, { 0x00000000, 0x17000000, 0x000 }, { 0x00000010, 0x00280a23, 0x000 }, { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, + { 0x00000000, 0x0ce00000, 0x0d0 }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x2b2 }, - { 0x00000000, 0x00400000, 0x0d6 }, - { 0x00000000, 0x00600000, 0x135 }, + { 0x00040000, 0x00694624, 0x2b4 }, + { 0x00000000, 0x00400000, 0x0d1 }, + { 0x00000000, 0x00600000, 0x130 }, { 0x00000000, 0x002820d0, 0x000 }, { 0x00000007, 0x00280a23, 0x000 }, { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0dd }, + { 0x00000000, 0x0ae00000, 0x0d8 }, { 0x00000000, 0x002f00a8, 0x000 }, - { 0x00000000, 0x04e00000, 0x0f6 }, - { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000000, 0x04e00000, 0x0f1 }, + { 0x00000000, 0x00400000, 0x0f8 }, { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0e2 }, + { 0x00000000, 0x0ae00000, 0x0dd }, { 0x00000000, 0x002f00a8, 0x000 }, - { 0x00000000, 0x02e00000, 0x0f6 }, - { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000000, 0x02e00000, 0x0f1 }, + { 0x00000000, 0x00400000, 0x0f8 }, { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0e7 }, + { 0x00000000, 0x0ae00000, 0x0e2 }, { 0x00000000, 0x002f00a8, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0f6 }, - { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000000, 0x0ce00000, 0x0f1 }, + { 0x00000000, 0x00400000, 0x0f8 }, { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0ec }, + { 0x00000000, 0x0ae00000, 0x0e7 }, { 0x00000000, 0x002f00a8, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0f6 }, - { 0x00000000, 0x00400000, 0x0fd }, - { 0x00000005, 0x002f0222, 0x000 }, { 0x00000000, 0x0ae00000, 0x0f1 }, + { 0x00000000, 0x00400000, 0x0f8 }, + { 0x00000005, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0ec }, { 0x00000000, 0x002f00a8, 0x000 }, - { 0x00000000, 0x06e00000, 0x0f6 }, - { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000000, 0x06e00000, 0x0f1 }, + { 0x00000000, 0x00400000, 0x0f8 }, { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0f6 }, + { 0x00000000, 0x0ae00000, 0x0f1 }, { 0x00000000, 0x002f00a8, 0x000 }, - { 0x00000000, 0x08e00000, 0x0f6 }, - { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000000, 0x08e00000, 0x0f1 }, + { 0x00000000, 0x00400000, 0x0f8 }, { 0x00007f00, 0x00280a21, 0x000 }, { 0x00004500, 0x002f0222, 0x000 }, { 0x00000000, 0x0ae00000, 0x000 }, { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14e00000, 0x11b }, + { 0x00000000, 0x14e00000, 0x116 }, { 0x00000000, 0xc0204400, 0x000 }, { 0x00000000, 0xc0404800, 0x000 }, { 0x00007f00, 0x00280a21, 0x000 }, { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x102 }, + { 0x00000000, 0x0ae00000, 0x0fd }, { 0x00000000, 0xc0200000, 0x000 }, { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c07, 0x0cd }, + { 0x00000000, 0x00404c07, 0x0c8 }, { 0x00000000, 0xc0201000, 0x000 }, { 0x00000000, 0xc0201400, 0x000 }, { 0x00000000, 0xc0201800, 0x000 }, @@ -304,11 +301,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x17000000, 0x000 }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00040000, 0x00694624, 0x2b4 }, { 0x00000000, 0x002820d0, 0x000 }, { 0x00000000, 0x002f00a8, 0x000 }, { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00404c07, 0x107 }, + { 0x00000000, 0x00404c07, 0x102 }, { 0x00000000, 0xc0201000, 0x000 }, { 0x00000000, 0xc0201400, 0x000 }, { 0x00000000, 0xc0201800, 0x000 }, @@ -316,11 +313,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x17000000, 0x000 }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00040000, 0x00694624, 0x2b4 }, { 0x00000000, 0x002820d0, 0x000 }, { 0x00000000, 0x002f00a8, 0x000 }, { 0x00000000, 0x06e00000, 0x000 }, - { 0x00000000, 0x00404c07, 0x113 }, + { 0x00000000, 0x00404c07, 0x10e }, { 0x0000060d, 0x00204411, 0x000 }, { 0x00000000, 0xc0204800, 0x000 }, { 0x0000860e, 0x00204411, 0x000 }, @@ -335,13 +332,13 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000001, 0x00204811, 0x000 }, { 0x00000000, 0xc0200800, 0x000 }, { 0x00007fff, 0x00281a22, 0x000 }, - { 0x00040000, 0x00694626, 0x2b2 }, + { 0x00040000, 0x00694626, 0x2b4 }, { 0x00000000, 0x00200c10, 0x000 }, { 0x00000000, 0xc0201000, 0x000 }, { 0x80000000, 0x00281a22, 0x000 }, { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0ce00000, 0x132 }, - { 0x00000000, 0x00600000, 0x135 }, + { 0x00000000, 0x0ce00000, 0x12d }, + { 0x00000000, 0x00600000, 0x130 }, { 0x00000000, 0x00201c10, 0x000 }, { 0x00000000, 0x00300c67, 0x000 }, { 0x0000060d, 0x00204411, 0x000 }, @@ -353,10 +350,10 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x00204811, 0x000 }, { 0x000001ea, 0x00204411, 0x000 }, { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x1ac00000, 0x13b }, + { 0x00000000, 0x1ac00000, 0x136 }, { 0x9e00ffff, 0x00204411, 0x000 }, { 0xdeadbeef, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x13e }, + { 0x00000000, 0x1ae00000, 0x139 }, { 0xa400ffff, 0x00204411, 0x000 }, { 0x00000000, 0x0080480b, 0x000 }, { 0x000001f3, 0x00204411, 0x000 }, @@ -405,28 +402,28 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000001, 0x00303e2f, 0x000 }, { 0x00000000, 0xc0200800, 0x000 }, { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x172 }, + { 0x00000000, 0x0ce00000, 0x16d }, { 0x00000000, 0xd9000000, 0x000 }, { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0x00600000, 0x287 }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000002, 0x00204811, 0x000 }, { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ae00000, 0x175 }, + { 0x00000000, 0x0ae00000, 0x170 }, { 0x00000000, 0xc0200800, 0x000 }, { 0x00000009, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x17d }, - { 0x00000000, 0x00600000, 0x2af }, + { 0x00000000, 0x14c00000, 0x178 }, + { 0x00000000, 0x00600000, 0x2aa }, { 0x00000000, 0x00200c11, 0x000 }, { 0x00000016, 0x00203623, 0x000 }, { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x180 }, + { 0x00000000, 0x14c00000, 0x17b }, { 0x00000000, 0xc0200000, 0x000 }, { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x183 }, + { 0x00000000, 0x14c00000, 0x17e }, { 0x00000000, 0xc0200000, 0x000 }, { 0x00000002, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x18d }, + { 0x00000000, 0x14c00000, 0x188 }, { 0x00000004, 0xc0203620, 0x000 }, { 0x00000005, 0xc0203620, 0x000 }, { 0x00000006, 0xc0203620, 0x000 }, @@ -436,7 +433,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x0000000a, 0xc0203620, 0x000 }, { 0x0000000b, 0xc0203620, 0x000 }, { 0x00000003, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b5 }, + { 0x00000000, 0x14c00000, 0x1b0 }, { 0x00000000, 0xc0200c00, 0x000 }, { 0x8c00ffff, 0x00204411, 0x000 }, { 0x00000000, 0x00204803, 0x000 }, @@ -476,24 +473,24 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000003, 0x00384a27, 0x000 }, { 0x00300000, 0x00293a2e, 0x000 }, { 0x00000004, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x1bd }, + { 0x00000000, 0x14c00000, 0x1b8 }, { 0xa300ffff, 0x00204411, 0x000 }, { 0x00000000, 0x40204800, 0x000 }, { 0x0000000a, 0xc0220e20, 0x000 }, { 0x00000011, 0x00203623, 0x000 }, { 0x000021f4, 0x00204411, 0x000 }, - { 0x0000000a, 0x00614a2c, 0x2af }, + { 0x0000000a, 0x00614a2c, 0x2aa }, { 0x00000005, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x1c0 }, + { 0x00000000, 0x14c00000, 0x1bb }, { 0x00000000, 0xc0200000, 0x000 }, { 0x00000006, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x1c6 }, + { 0x00000000, 0x14c00000, 0x1c1 }, { 0x9c00ffff, 0x00204411, 0x000 }, { 0x0000001f, 0x40214a20, 0x000 }, { 0x9600ffff, 0x00204411, 0x000 }, { 0x00000000, 0xc0204800, 0x000 }, { 0x00000007, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x1d0 }, + { 0x00000000, 0x14c00000, 0x1cb }, { 0x3fffffff, 0x00283a2e, 0x000 }, { 0xc0000000, 0x40280e20, 0x000 }, { 0x00000000, 0x0029386e, 0x000 }, @@ -503,7 +500,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0xc0202c00, 0x000 }, { 0x00000000, 0x0020480b, 0x000 }, { 0x00000008, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x1dc }, + { 0x00000000, 0x14c00000, 0x1d7 }, { 0x00000000, 0xc0200c00, 0x000 }, { 0x00000013, 0x00203623, 0x000 }, { 0x00000015, 0x00203623, 0x000 }, @@ -515,7 +512,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0xefffffff, 0x00283a2e, 0x000 }, { 0x00000000, 0x0029386e, 0x000 }, { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0x00600000, 0x287 }, { 0x00000000, 0xc0200800, 0x000 }, { 0x0000001f, 0x00210e22, 0x000 }, { 0x00000000, 0x14e00000, 0x000 }, @@ -529,46 +526,46 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x8400ffff, 0x00204411, 0x000 }, { 0x00000000, 0x00204803, 0x000 }, { 0x00000000, 0x21000000, 0x000 }, - { 0x00000000, 0x00400000, 0x1de }, + { 0x00000000, 0x00400000, 0x1d9 }, { 0x8200ffff, 0x00204411, 0x000 }, { 0x00000001, 0x00204811, 0x000 }, { 0x00000000, 0xc0200800, 0x000 }, { 0x00003fff, 0x40280e20, 0x000 }, { 0x00000010, 0xc0211220, 0x000 }, { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x1fb }, - { 0x00000000, 0x2ae00000, 0x205 }, + { 0x00000000, 0x0ae00000, 0x1f6 }, + { 0x00000000, 0x2ae00000, 0x200 }, { 0x20000080, 0x00281e2e, 0x000 }, { 0x00000080, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000000, 0x00401c0c, 0x1f9 }, + { 0x00000000, 0x0ce00000, 0x1f3 }, + { 0x00000000, 0x00401c0c, 0x1f4 }, { 0x00000010, 0x00201e2d, 0x000 }, { 0x000021f9, 0x00294627, 0x000 }, - { 0x00000000, 0x00404811, 0x205 }, + { 0x00000000, 0x00404811, 0x200 }, { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x23a }, - { 0x00000000, 0x28e00000, 0x205 }, + { 0x00000000, 0x0ae00000, 0x235 }, + { 0x00000000, 0x28e00000, 0x200 }, { 0x00800080, 0x00281e2e, 0x000 }, { 0x00000080, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x202 }, - { 0x00000000, 0x00401c0c, 0x203 }, + { 0x00000000, 0x0ce00000, 0x1fd }, + { 0x00000000, 0x00401c0c, 0x1fe }, { 0x00000010, 0x00201e2d, 0x000 }, { 0x000021f9, 0x00294627, 0x000 }, { 0x00000001, 0x00204811, 0x000 }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x20c }, + { 0x00000000, 0x0ae00000, 0x207 }, { 0x00000003, 0x00204811, 0x000 }, { 0x0000000c, 0x0020162d, 0x000 }, { 0x0000000d, 0x00201a2d, 0x000 }, - { 0xffdfffff, 0x00483a2e, 0x210 }, + { 0xffdfffff, 0x00483a2e, 0x20b }, { 0x00000004, 0x00204811, 0x000 }, { 0x0000000e, 0x0020162d, 0x000 }, { 0x0000000f, 0x00201a2d, 0x000 }, { 0xffefffff, 0x00283a2e, 0x000 }, { 0x00000000, 0x00201c10, 0x000 }, { 0x00000000, 0x002f0067, 0x000 }, - { 0x00000000, 0x04e00000, 0x205 }, + { 0x00000000, 0x04e00000, 0x200 }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000006, 0x00204811, 0x000 }, { 0x8300ffff, 0x00204411, 0x000 }, @@ -578,10 +575,10 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x8400ffff, 0x00204411, 0x000 }, { 0x00000000, 0x00204803, 0x000 }, { 0x00000000, 0x21000000, 0x000 }, - { 0x00000000, 0x00601010, 0x28c }, + { 0x00000000, 0x00601010, 0x287 }, { 0x0000000c, 0x00221e24, 0x000 }, { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x22d }, + { 0x00000000, 0x0ae00000, 0x228 }, { 0x20000000, 0x00293a2e, 0x000 }, { 0x000021f7, 0x0029462c, 0x000 }, { 0x00000000, 0x002948c7, 0x000 }, @@ -594,7 +591,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x00204803, 0x000 }, { 0x00000000, 0x23000000, 0x000 }, { 0x8d00ffff, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x240 }, + { 0x00000000, 0x00404803, 0x23b }, { 0x00800000, 0x00293a2e, 0x000 }, { 0x000021f6, 0x0029462c, 0x000 }, { 0x00000000, 0x002948c7, 0x000 }, @@ -607,7 +604,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x00204803, 0x000 }, { 0x00000000, 0x25000000, 0x000 }, { 0x8e00ffff, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x240 }, + { 0x00000000, 0x00404803, 0x23b }, { 0x8300ffff, 0x00204411, 0x000 }, { 0x00000003, 0x00381224, 0x000 }, { 0x00005000, 0x00304a24, 0x000 }, @@ -621,37 +618,37 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000001, 0x00204811, 0x000 }, { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24a }, + { 0x00000000, 0x0ae00000, 0x245 }, { 0x000021f6, 0x0029122c, 0x000 }, - { 0x00040000, 0x00494624, 0x24c }, + { 0x00040000, 0x00494624, 0x247 }, { 0x000021f7, 0x0029122c, 0x000 }, { 0x00040000, 0x00294624, 0x000 }, - { 0x00000000, 0x00600000, 0x2b2 }, + { 0x00000000, 0x00600000, 0x2b4 }, { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x252 }, + { 0x00000000, 0x0ce00000, 0x24d }, { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x252 }, - { 0x00000000, 0x00481630, 0x258 }, + { 0x00000000, 0x0ce00000, 0x24d }, + { 0x00000000, 0x00481630, 0x253 }, { 0x00000fff, 0x00281630, 0x000 }, { 0x0000000c, 0x00211a30, 0x000 }, { 0x00000fff, 0x00281a26, 0x000 }, { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0ae00000, 0x258 }, + { 0x00000000, 0x0ae00000, 0x253 }, { 0x00000000, 0xc0400000, 0x000 }, - { 0x00040d02, 0x00604411, 0x2b2 }, + { 0x00040d02, 0x00604411, 0x2b4 }, { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x25d }, + { 0x00000000, 0x0ae00000, 0x258 }, { 0x00000010, 0x00211e30, 0x000 }, - { 0x00000fff, 0x00482630, 0x267 }, + { 0x00000fff, 0x00482630, 0x262 }, { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x261 }, + { 0x00000000, 0x0ae00000, 0x25c }, { 0x00000fff, 0x00281e30, 0x000 }, - { 0x00000200, 0x00402411, 0x267 }, + { 0x00000200, 0x00402411, 0x262 }, { 0x00000000, 0x00281e30, 0x000 }, { 0x00000010, 0x00212630, 0x000 }, { 0x00000010, 0x00211a30, 0x000 }, { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0ae00000, 0x258 }, + { 0x00000000, 0x0ae00000, 0x253 }, { 0x00000000, 0xc0400000, 0x000 }, { 0x00000003, 0x00381625, 0x000 }, { 0x00000003, 0x00381a26, 0x000 }, @@ -662,13 +659,13 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0xc0204800, 0x000 }, { 0x00000000, 0x00204806, 0x000 }, { 0x00005000, 0x00302225, 0x000 }, - { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00040000, 0x00694628, 0x2b4 }, { 0x00000001, 0x00302228, 0x000 }, { 0x00000000, 0x00202810, 0x000 }, - { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00040000, 0x00694628, 0x2b4 }, { 0x00000001, 0x00302228, 0x000 }, { 0x00000000, 0x00200810, 0x000 }, - { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00040000, 0x00694628, 0x2b4 }, { 0x00000001, 0x00302228, 0x000 }, { 0x00000000, 0x00201410, 0x000 }, { 0x0000060d, 0x00204411, 0x000 }, @@ -678,35 +675,42 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x00204802, 0x000 }, { 0x00000000, 0x00204805, 0x000 }, { 0x00000000, 0x002f0128, 0x000 }, - { 0x00000000, 0x0ae00000, 0x282 }, + { 0x00000000, 0x0ae00000, 0x27d }, { 0x00005000, 0x00302227, 0x000 }, { 0x0000000c, 0x00300e23, 0x000 }, { 0x00000003, 0x00331a26, 0x000 }, { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0ae00000, 0x270 }, + { 0x00000000, 0x0ae00000, 0x26b }, { 0x00000000, 0x00400000, 0x000 }, { 0x000001f3, 0x00204411, 0x000 }, { 0x04000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x289 }, - { 0x00000000, 0xc0600000, 0x28c }, + { 0x00000000, 0x00400000, 0x284 }, + { 0x00000000, 0xc0600000, 0x287 }, { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0x0ec00000, 0x28e }, + { 0x00000000, 0x0ec00000, 0x289 }, { 0x00000000, 0x00800000, 0x000 }, { 0x000021f9, 0x0029462c, 0x000 }, { 0x00000005, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x0000000a, 0x0021262c, 0x000 }, + { 0x00000000, 0x00210130, 0x000 }, + { 0x00000000, 0x14c00000, 0x292 }, + { 0xa500ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00404811, 0x28e }, { 0x00000000, 0x0020280c, 0x000 }, { 0x00000011, 0x0020262d, 0x000 }, { 0x00000000, 0x002f012c, 0x000 }, - { 0x00000000, 0x0ae00000, 0x295 }, - { 0x00000000, 0x00403011, 0x296 }, + { 0x00000000, 0x0ae00000, 0x297 }, + { 0x00000000, 0x00403011, 0x298 }, { 0x00000400, 0x0030322c, 0x000 }, { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000002, 0x00204811, 0x000 }, { 0x0000000a, 0x0021262c, 0x000 }, { 0x00000000, 0x00210130, 0x000 }, - { 0x00000000, 0x14c00000, 0x29d }, + { 0x00000000, 0x14c00000, 0x29f }, { 0xa500ffff, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x299 }, + { 0x00000001, 0x00404811, 0x29b }, { 0xa500ffff, 0x00204411, 0x000 }, { 0x00000000, 0x00204811, 0x000 }, { 0x000021f4, 0x0029462c, 0x000 }, @@ -718,6 +722,8 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x00210130, 0x000 }, { 0xdf7fffff, 0x00283a2e, 0x000 }, { 0x00000010, 0x0080362a, 0x000 }, + { 0x00000000, 0x00203011, 0x000 }, + { 0x00000010, 0x0080362c, 0x000 }, { 0x9700ffff, 0x00204411, 0x000 }, { 0x00000000, 0x0020480c, 0x000 }, { 0xa200ffff, 0x00204411, 0x000 }, @@ -725,13 +731,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x8100ffff, 0x00204411, 0x000 }, { 0x00000002, 0x00204811, 0x000 }, { 0x00000000, 0x00810130, 0x000 }, - { 0x00000000, 0x00203011, 0x000 }, - { 0x00000010, 0x0080362c, 0x000 }, { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x2b2 }, + { 0x00000000, 0x1ac00000, 0x2b4 }, { 0x9f00ffff, 0x00204411, 0x000 }, { 0xdeadbeef, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x2b5 }, + { 0x00000000, 0x1ae00000, 0x2b7 }, { 0x00000000, 0x00800000, 0x000 }, { 0x00000000, 0x00000000, 0x000 }, { 0x00000000, 0x00000000, 0x000 }, @@ -776,28 +780,26 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00000000, 0x00000000, 0x000 }, { 0x00000000, 0x00000000, 0x000 }, { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00020143, 0x00020002, 0x000 }, + { 0x0002013e, 0x00020002, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, - { 0x00020002, 0x01dd0002, 0x000 }, - { 0x006301ee, 0x00280012, 0x000 }, + { 0x00020002, 0x01d80002, 0x000 }, + { 0x005e01e9, 0x00280012, 0x000 }, { 0x00020002, 0x00020026, 0x000 }, - { 0x00020002, 0x01ec0002, 0x000 }, - { 0x00790242, 0x00020002, 0x000 }, + { 0x00020002, 0x01e70002, 0x000 }, + { 0x0074023d, 0x00020002, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, { 0x00200012, 0x00020016, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, - { 0x011b00c5, 0x00020125, 0x000 }, - { 0x00020141, 0x00020002, 0x000 }, - { 0x00c50002, 0x0143002e, 0x000 }, - { 0x00a2016b, 0x00020145, 0x000 }, - { 0x00020002, 0x01200002, 0x000 }, - { 0x00020002, 0x010f0103, 0x000 }, + { 0x011600c0, 0x00020120, 0x000 }, + { 0x0002013c, 0x00020002, 0x000 }, + { 0x00c00002, 0x013e002e, 0x000 }, + { 0x009d0166, 0x00020140, 0x000 }, + { 0x00020002, 0x011b0002, 0x000 }, + { 0x00020002, 0x010a00fe, 0x000 }, { 0x00090002, 0x000e000e, 0x000 }, - { 0x0058003d, 0x00600002, 0x000 }, - { 0x000200c1, 0x0002028a, 0x000 }, + { 0x0049003d, 0x005b0002, 0x000 }, + { 0x000200bc, 0x00020285, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, @@ -805,7 +807,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ { 0x00020002, 0x00020002, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, { 0x00020002, 0x00020002, 0x000 }, - { 0x000502b1, 0x00020008, 0x000 }, + { 0x000502b3, 0x00020008, 0x000 }, }; #endif diff --git a/drivers/mxc/amd-gpu/include/gsl_buildconfig.h b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h index 4e6be4da7dc4..73be13c4a725 100644 --- a/drivers/mxc/amd-gpu/include/gsl_buildconfig.h +++ b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h @@ -27,7 +27,7 @@ */ /* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ #ifndef __GSL__BUILDCONFIG_H @@ -49,7 +49,7 @@ /* #define GSL_MMU_PAGETABLE_PERPROCESS */ -#define GSL_CALLER_PROCESS_MAX 10 +#define GSL_CALLER_PROCESS_MAX 64 #define GSL_SHMEM_MAX_APERTURES 3 #endif /* __GSL__BUILDCONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_halconfig.h b/drivers/mxc/amd-gpu/include/gsl_halconfig.h index 363474b7a6bb..17e61a37f297 100644 --- a/drivers/mxc/amd-gpu/include/gsl_halconfig.h +++ b/drivers/mxc/amd-gpu/include/gsl_halconfig.h @@ -27,7 +27,7 @@ */ /* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ #ifndef __GSL_HALCONFIG_H @@ -38,7 +38,7 @@ #define GSL_HAL_SIZE_REG_G12 0x00001000 /* 4KB */ -#define GSL_HAL_SHMEM_SIZE_EMEM1_MMU 0x01800000 /* 24MB */ +#define GSL_HAL_SHMEM_SIZE_EMEM1_MMU 0x08000000 /* 128MB */ #define GSL_HAL_SHMEM_SIZE_EMEM2_MMU 0x00400000 /* 4MB */ #define GSL_HAL_SHMEM_SIZE_PHYS_MMU 0x00400000 /* 4MB */ diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c index 51270ada4d36..a0e196123022 100644 --- a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c @@ -1,5 +1,5 @@ /* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,7 +18,7 @@ */ /* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ #include "gsl_hal.h" @@ -49,6 +49,7 @@ extern int gmem_size; extern phys_addr_t gpu_reserved_mem; extern int gpu_reserved_mem_size; extern int gpu_2d_irq, gpu_3d_irq; +extern int enable_mmu; KGSLHAL_API int @@ -121,8 +122,7 @@ kgsl_hal_init(void) hal->has_z160 = 0; } - /* there is still some problem to enable mmu currently */ - gsl_driver.enable_mmu = 0; + gsl_driver.enable_mmu = enable_mmu; /* setup register space */ if (hal->has_z430) { diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h index 305b2ee9066d..96abace9b736 100644 --- a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h @@ -43,8 +43,6 @@ kgsl_hwaccess_memread(void *dst, unsigned int gpubase, unsigned int gpuoffset, u if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { gsl_linux_map_read(dst, gpubase+gpuoffset, sizebytes, touserspace); } else { - mb(); - dsb(); if (touserspace) { if (copy_to_user(dst, (void *)(gpubase + gpuoffset), sizebytes)) @@ -56,8 +54,6 @@ kgsl_hwaccess_memread(void *dst, unsigned int gpubase, unsigned int gpuoffset, u { kos_memcpy(dst, (void *) (gpubase + gpuoffset), sizebytes); } - mb(); - dsb(); } } @@ -69,8 +65,6 @@ kgsl_hwaccess_memwrite(unsigned int gpubase, unsigned int gpuoffset, void *src, if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { gsl_linux_map_write(src, gpubase+gpuoffset, sizebytes, fromuserspace); } else { - mb(); - dsb(); if (fromuserspace) { if (copy_from_user((void *)(gpubase + gpuoffset), src, sizebytes)) @@ -82,8 +76,6 @@ kgsl_hwaccess_memwrite(unsigned int gpubase, unsigned int gpuoffset, void *src, { kos_memcpy((void *)(gpubase + gpuoffset), src, sizebytes); } - mb(); - dsb(); } } @@ -95,11 +87,7 @@ kgsl_hwaccess_memset(unsigned int gpubase, unsigned int gpuoffset, unsigned int if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { gsl_linux_map_set(gpuoffset+gpubase, value, sizebytes); } else { - mb(); - dsb(); kos_memset((void *)(gpubase + gpuoffset), value, sizebytes); - mb(); - dsb(); } } @@ -115,11 +103,7 @@ kgsl_hwaccess_regread(gsl_deviceid_t device_id, unsigned int gpubase, unsigned i reg = (unsigned int *)(gpubase + (offsetwords << 2)); - mb(); - dsb(); - *data = __raw_readl(reg); - mb(); - dsb(); + *data = readl(reg); } //---------------------------------------------------------------------------- @@ -133,10 +117,6 @@ kgsl_hwaccess_regwrite(gsl_deviceid_t device_id, unsigned int gpubase, unsigned (void) device_id; reg = (unsigned int *)(gpubase + (offsetwords << 2)); - mb(); - dsb(); - __raw_writel(data, reg); - mb(); - dsb(); + writel(data, reg); } #endif // __GSL_HWACCESS_WINCE_MX51_H diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c index b67404150e10..2e6bc55e88fe 100644 --- a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c @@ -1,5 +1,5 @@ /* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -40,6 +40,7 @@ #include <linux/uaccess.h> #include <mach/mxc_gpu.h> +#include <linux/fsl_devices.h> int gpu_2d_irq, gpu_3d_irq; @@ -51,6 +52,7 @@ int gmem_size; phys_addr_t gpu_reserved_mem; int gpu_reserved_mem_size; int z160_version; +int enable_mmu; static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr); static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr); @@ -769,14 +771,15 @@ static int gpu_probe(struct platform_device *pdev) int i; struct resource *res; struct device *dev; - struct mxc_gpu_platform_data *pdata; + struct mxc_gpu_platform_data *gpu_data = NULL; - pdata = pdev->dev.platform_data; - if (pdata) { - z160_version = pdata->z160_revision; - gpu_reserved_mem = pdata->reserved_mem_base; - gpu_reserved_mem_size = pdata->reserved_mem_size; - } + gpu_data = (struct mxc_gpu_platform_data *)pdev->dev.platform_data; + + if (gpu_data == NULL) + return 0; + + z160_version = gpu_data->z160_revision; + enable_mmu = gpu_data->enable_mmu; for(i = 0; i < 2; i++){ res = platform_get_resource(pdev, IORESOURCE_IRQ, i); @@ -795,8 +798,8 @@ static int gpu_probe(struct platform_device *pdev) } } - for (i = 0; i < 3; i++) { - res = platform_get_resource(pdev, IORESOURCE_MEM, i); + for (i = 0; i < 4; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); if (!res) { gpu_2d_regbase = 0; gpu_2d_regsize = 0; @@ -807,14 +810,17 @@ static int gpu_probe(struct platform_device *pdev) gpu_reserved_mem_size = 0; break; }else{ - if(strcmp(res->name, "gpu_2d_registers") == 0){ - gpu_2d_regbase = res->start; - gpu_2d_regsize = res->end - res->start + 1; - }else if(strcmp(res->name, "gpu_3d_registers") == 0){ - gpu_3d_regbase = res->start; - gpu_3d_regsize = res->end - res->start + 1; - }else if(strcmp(res->name, "gpu_graphics_mem") == 0){ - gmem_size = res->end - res->start + 1; + if (strcmp(res->name, "gpu_2d_registers") == 0) { + gpu_2d_regbase = res->start; + gpu_2d_regsize = res->end - res->start + 1; + } else if (strcmp(res->name, "gpu_3d_registers") == 0) { + gpu_3d_regbase = res->start; + gpu_3d_regsize = res->end - res->start + 1; + } else if (strcmp(res->name, "gpu_graphics_mem") == 0) { + gmem_size = res->end - res->start + 1; + } else if (strcmp(res->name, "gpu_reserved_mem") == 0) { + gpu_reserved_mem = res->start; + gpu_reserved_mem_size = res->end - res->start + 1; } } } diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c index 3685a5756baf..911469b720d7 100644 --- a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c @@ -173,10 +173,13 @@ int del_all_memblocks_from_allocated_list(struct file *fd) printk(KERN_INFO "Not all allocated memory blocks were freed. Doing it now.\n"); list_for_each_entry_safe(cursor, next, head, node) { - printk(KERN_INFO "Freeing list entry #%u, gpuaddr=%x\n", (u32)cursor->allocation_number, cursor->allocated_block.gpuaddr); - kgsl_sharedmem_free(&cursor->allocated_block); - list_del(&cursor->node); - kfree(cursor); + printk(KERN_DEBUG "Freeing list entry #%u, gpuaddr=%x\n", + (u32)cursor->allocation_number, + cursor->allocated_block.gpuaddr); + + kgsl_sharedmem_free(&cursor->allocated_block); + list_del(&cursor->node); + kfree(cursor); } } diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c index 7fee7b814411..3c1e02e5bc42 100644 --- a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c @@ -61,7 +61,7 @@ void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size) } } - va = __vmalloc(size, GFP_KERNEL, pgprot_noncached(pgprot_kernel)); + va = __vmalloc(size, GFP_KERNEL, pgprot_writecombine(pgprot_kernel)); if(va == NULL){ mutex_unlock(&gsl_linux_map_mutex); return NULL; diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/misc.c b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c index b3a4582bb156..db7b8cf3a2d1 100644 --- a/drivers/mxc/amd-gpu/platform/hal/linux/misc.c +++ b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -38,9 +38,9 @@ typedef struct _gsl_autogate_t { } gsl_autogate_t; static gsl_autogate_t *g_autogate[2]; -static DEFINE_SEMAPHORE(sem_dev); +static DEFINE_MUTEX(sem_dev); -#define KGSL_DEVICE_IDLE_TIMEOUT 5000 /* unit ms */ +#define KGSL_DEVICE_IDLE_TIMEOUT 2000 /* unit ms */ static void clk_disable_task(struct work_struct *work) { @@ -79,10 +79,10 @@ static int _kgsl_device_active(gsl_device_t *dev, int all) int index; index = autogate->dev->id == GSL_DEVICE_G12 ? GSL_DEVICE_YAMATO - 1 : GSL_DEVICE_G12 - 1; - down(&sem_dev); + mutex_lock(&sem_dev); if (g_autogate[index]) _kgsl_device_active(g_autogate[index]->dev, 0); - up(&sem_dev); + mutex_unlock(&sem_dev); } return 0; } @@ -99,7 +99,6 @@ static void kgsl_device_inactive(unsigned long data) // printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, autogate->dev->id, autogate->active); del_timer(&autogate->timer); spin_lock_irqsave(&autogate->lock, flags); - WARN(!autogate->active, "GPU Device %d is already inactive\n", autogate->dev->id); if (autogate->active) { autogate->active = 0; autogate->pending = 1; @@ -137,7 +136,7 @@ int kgsl_device_autogate_init(gsl_device_t *dev) printk(KERN_ERR "%s: out of memory!\n", __func__); return -ENOMEM; } - down(&sem_dev); + mutex_lock(&sem_dev); autogate->dev = dev; autogate->active = 1; spin_lock_init(&autogate->lock); @@ -150,7 +149,7 @@ int kgsl_device_autogate_init(gsl_device_t *dev) INIT_WORK(&autogate->dis_task, clk_disable_task); dev->autogate = autogate; g_autogate[dev->id - 1] = autogate; - up(&sem_dev); + mutex_unlock(&sem_dev); return 0; } @@ -159,13 +158,13 @@ void kgsl_device_autogate_exit(gsl_device_t *dev) gsl_autogate_t *autogate = dev->autogate; // printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active); - down(&sem_dev); + mutex_lock(&sem_dev); del_timer_sync(&autogate->timer); if (!autogate->active) kgsl_clock(autogate->dev->id, 1); flush_work(&autogate->dis_task); g_autogate[dev->id - 1] = NULL; - up(&sem_dev); + mutex_unlock(&sem_dev); kfree(autogate); dev->autogate = NULL; } diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index 61687ad1411c..0fab6f95a7ef 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -514,6 +514,10 @@ static int __devinit ipu_probe(struct platform_device *pdev) /* Set sync refresh channels and CSI->mem channel as high priority */ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0)); + /* AXI burst setting for sync refresh channels */ + if (g_ipu_hw_rev == 3) + ipu_idmac_write(ipu, 0x003F0000, IDMAC_CH_LOCK_EN_1); + /* Set MCU_T to divide MCU access window into 2 */ ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); @@ -1170,6 +1174,13 @@ void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel) if (_ipu_is_primary_disp_chan(in_dma)) clk_disable(&ipu->pixel_clk[ipu->dc_di_assignment[dc_chan]]); + /* Restore IDMAC_LOCK_EN when we don't use dual display */ + /* and the video mode for single display is not tough */ + if (!(ipu->di_use_count[0] && ipu->di_use_count[1]) && + dmfc_type_setup != DMFC_HIGH_RESOLUTION_ONLY_DP && + _ipu_is_dmfc_chan(in_dma) && g_ipu_hw_rev == 3) + ipu_idmac_write(ipu, 0x003F0000, IDMAC_CH_LOCK_EN_1); + _ipu_unlock(ipu); _ipu_put(ipu); @@ -2136,6 +2147,16 @@ int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel) ipu_conf |= IPU_CONF_SMFC_EN; ipu_cm_write(ipu, ipu_conf, IPU_CONF); + /* Clear IDMAC_LOCK_EN to workaround black flash for dual display */ + /* and for tough video mode of single display */ + if (g_ipu_hw_rev == 3 && _ipu_is_dmfc_chan(in_dma)) { + if ((ipu->di_use_count[1] && ipu->di_use_count[0]) || + (dmfc_type_setup == DMFC_HIGH_RESOLUTION_ONLY_DP)) + ipu_idmac_write(ipu, 0x0, IDMAC_CH_LOCK_EN_1); + else + ipu_idmac_write(ipu, 0x003F0000, IDMAC_CH_LOCK_EN_1); + } + if (idma_is_valid(in_dma)) { reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma)); ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); @@ -3116,6 +3137,11 @@ static int ipu_resume_noirq(struct device *dev) _ipu_init_dc_mappings(ipu); /* Set sync refresh channels as high priority */ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0)); + + /* AXI burst setting for sync refresh channels */ + if (g_ipu_hw_rev == 3) + ipu_idmac_write(ipu, 0x003F0000, IDMAC_CH_LOCK_EN_1); + _ipu_put(ipu); } diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c index 6810cea8f503..7b269b8d5ecb 100644 --- a/drivers/mxc/ipu3/ipu_device.c +++ b/drivers/mxc/ipu3/ipu_device.c @@ -1044,9 +1044,9 @@ static int check_task(struct ipu_task_entry *t) t->output.crop.h = tmp; } + /* if mode is NULL, then allow blit copy using image converter */ if (t->set.mode == NULL_MODE) { - ret = IPU_CHECK_ERR_PROC_NO_NEED; - goto done; + t->set.mode |= IC_MODE; } if ((t->set.i_uoff % 8) || (t->set.i_voff % 8)) @@ -2985,7 +2985,7 @@ static int ipu_task_thread(void *argv) }; int ret; int curr_thread_id; - uint32_t size; + uint32_t size = 0; unsigned long flags; unsigned int cpu; struct cpumask cpu_mask; diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c index d2fa65dd774e..056726f80989 100644 --- a/drivers/mxc/ipu3/ipu_disp.c +++ b/drivers/mxc/ipu3/ipu_disp.c @@ -206,6 +206,7 @@ struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2] = { .con_id = "pixel_clk_1", }, }, +#ifdef CONFIG_MXC_IPU_V3H { { .con_id = "pixel_clk_0", @@ -214,6 +215,7 @@ struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2] = { .con_id = "pixel_clk_1", }, }, +#endif }; int dmfc_type_setup; diff --git a/drivers/mxc/pmic/core/pmic_core_i2c.c b/drivers/mxc/pmic/core/pmic_core_i2c.c index 09172b387b0e..9033f76fb077 100644 --- a/drivers/mxc/pmic/core/pmic_core_i2c.c +++ b/drivers/mxc/pmic/core/pmic_core_i2c.c @@ -256,7 +256,7 @@ static int __devinit pmic_probe(struct i2c_client *client, /* Set and install PMIC IRQ handler */ - set_irq_type(pmic_irq, IRQF_TRIGGER_HIGH); + irq_set_irq_type(pmic_irq, IRQF_TRIGGER_HIGH); ret = request_irq(pmic_irq, pmic_irq_handler, 0, "PMIC_IRQ", diff --git a/drivers/mxc/pmic/core/pmic_core_spi.c b/drivers/mxc/pmic/core/pmic_core_spi.c index f02b42749791..48c99b28c73f 100644 --- a/drivers/mxc/pmic/core/pmic_core_spi.c +++ b/drivers/mxc/pmic/core/pmic_core_spi.c @@ -198,7 +198,7 @@ static int __devinit pmic_probe(struct spi_device *spi) } /* Set and install PMIC IRQ handler */ - set_irq_type(spi->irq, IRQF_TRIGGER_HIGH); + irq_set_irq_type(spi->irq, IRQF_TRIGGER_HIGH); ret = request_irq(spi->irq, pmic_irq_handler, 0, "PMIC_IRQ", 0); if (ret) { kfree(spi_get_drvdata(spi)); diff --git a/drivers/net/fec.c b/drivers/net/fec.c index 6e710e11f1a4..877f99f94901 100755..100644 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c @@ -59,6 +59,7 @@ #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) #define FEC_ALIGNMENT 0xf +#define FEC_RX_FIFO_BR 0x480 #else #define FEC_ALIGNMENT 0x3 #endif @@ -286,14 +287,13 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) unsigned long estatus; unsigned long flags; - spin_lock_irqsave(&fep->hw_lock, flags); if (!fep->link) { /* Link is down or autonegotiation is in progress. */ netif_stop_queue(ndev); - spin_unlock_irqrestore(&fep->hw_lock, flags); return NETDEV_TX_BUSY; } + spin_lock_irqsave(&fep->hw_lock, flags); /* Fill in a Tx ring entry */ bdp = fep->cur_tx; @@ -395,8 +395,7 @@ fec_timeout(struct net_device *ndev) ndev->stats.tx_errors++; fec_restart(ndev, fep->full_duplex); - if (fep->link && !fep->tx_full) - netif_wake_queue(ndev); + netif_wake_queue(ndev); } static void @@ -565,8 +564,11 @@ static int fec_rx_poll(struct napi_struct *napi, int budget) ndev->stats.rx_frame_errors++; if (status & BD_ENET_RX_CR) /* CRC Error */ ndev->stats.rx_crc_errors++; - if (status & BD_ENET_RX_OV) /* FIFO overrun */ + if (status & BD_ENET_RX_OV) { /* FIFO overrun */ ndev->stats.rx_fifo_errors++; + writel(readl(fep->hwp + FEC_X_CNTRL) | 0x8 , fep->hwp + FEC_X_CNTRL); + goto rx_processing_done; + } } /* Report late collisions as a frame error. @@ -915,8 +917,10 @@ static void fec_enet_adjust_link(struct net_device *ndev) fep->link = phy_dev->link; if (phy_dev->link) { fec_restart(ndev, phy_dev->duplex); - if (!fep->tx_full) + if (netif_queue_stopped(ndev)) { + netif_start_queue(ndev); netif_wake_queue(ndev); + } } else fec_stop(ndev); status_change = 1; @@ -1088,7 +1092,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) */ fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), - (FEC_ENET_MII_CLK << 2)) << 1; + (FEC_ENET_MII_CLK << 1)) << 1; /* set hold time to 2 internal clock cycle */ if (cpu_is_mx6()) @@ -1566,6 +1570,11 @@ fec_restart(struct net_device *dev, int duplex) writel(0, fep->hwp + FEC_HASH_TABLE_LOW); #endif + /* FIXME: adjust RX FIFO size for performance*/ +#ifdef CONFIG_ARCH_MX53 + writel(FEC_RX_FIFO_BR, fep->hwp + FEC_R_FSTART); +#endif + /* Set maximum receive buffer size. */ writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); @@ -1589,8 +1598,10 @@ fec_restart(struct net_device *dev, int duplex) /* Enable MII mode */ if (duplex) { /* MII enable / FD enable */ - writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); + writel(OPT_FRAME_SIZE | 0x24, fep->hwp + FEC_R_CNTRL); writel(0x04, fep->hwp + FEC_X_CNTRL); + /* Set the RX Pause frame Interval */ + writel(0x1ffff, fep->hwp + FEC_OPD); } else { /* MII enable / No Rcv on Xmit */ writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); @@ -1623,6 +1634,7 @@ fec_restart(struct net_device *dev, int duplex) val |= (1 << 9); writel(val, fep->hwp + FEC_R_CNTRL); + } if (fep->ptimer_present) { /* Set Timer count */ @@ -1656,7 +1668,6 @@ fec_restart(struct net_device *dev, int duplex) writel(2, fep->hwp + FEC_MIIGSK_ENR); } #endif - } /* ENET enable */ val = reg | (0x1 << 1); diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 8145ff85c8ab..e6655b441abd 100755 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -149,6 +149,13 @@ config BATTERY_DA9030 Say Y here to enable support for batteries charger integrated into DA9030 PMIC. +config BATTERY_MAX17085 + tristate "Maxim MAX17085 charger" + depends on PMIC_DA9052 && SENSORS_DA9052 + help + Say Y to include support for the battery on the MAX17085. This + is dependent on DA9052 sensor. + config BATTERY_MAX17040 tristate "Maxim MAX17040 Fuel Gauge" depends on I2C diff --git a/drivers/power/Makefile b/drivers/power/Makefile index ad6493affec8..f9cadb161216 100755 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_CHARGER_MAX8903) += max8903_charger.o obj-$(CONFIG_CHARGER_TWL4030) += twl4030_charger.o obj-$(CONFIG_CHARGER_GPIO) += gpio-charger.o obj-$(CONFIG_BATTERY_DA9052) += da9052-battery.o +obj-$(CONFIG_BATTERY_MAX17085) += max17085_battery.o diff --git a/drivers/power/max17085_battery.c b/drivers/power/max17085_battery.c new file mode 100644 index 000000000000..f41d31352293 --- /dev/null +++ b/drivers/power/max17085_battery.c @@ -0,0 +1,399 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * MAX17085 Battery driver + */ + +#include <linux/module.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/power_supply.h> +#include <linux/jiffies.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <mach/gpio.h> + +struct max17085_chip { + struct device *dev; + + /*gpio*/ + int pwr_good; + int ac_in; + int charge_now; + int charge_done; + + struct power_supply ac; + struct power_supply bat; + struct delayed_work work; + + int online; + int health; + int status; + int voltage_uV; + int cap; +}; + +#define MAX17085_DELAY 3000 +#define MAX17085_DEF_TEMP 30 + +static int max17085_bat_get_mfr(struct power_supply *psy, + union power_supply_propval *val) +{ + val->strval = "unknown"; + return 0; +} + +static int max17085_bat_get_tech(struct power_supply *psy, + union power_supply_propval *val) +{ + val->intval = POWER_SUPPLY_TECHNOLOGY_LION; + return 0; +} + +static int max17085_bat_get_cap(struct power_supply *psy, + union power_supply_propval *val) +{ + struct max17085_chip *chip = container_of(psy, + struct max17085_chip, bat); + + val->intval = chip->cap; + return 0; +} + +static int max17085_bat_get_volt(struct power_supply *psy, + union power_supply_propval *val) +{ + struct max17085_chip *chip = container_of(psy, + struct max17085_chip, bat); + + val->intval = chip->voltage_uV; + return 0; +} + +static int max17085_bat_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + int ret = 0; + struct max17085_chip *chip = container_of(psy, + struct max17085_chip, bat); + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + val->intval = chip->status; + break; + case POWER_SUPPLY_PROP_HEALTH: + val->intval = chip->health; + break; + case POWER_SUPPLY_PROP_CAPACITY: + ret = max17085_bat_get_cap(psy, val); + if (ret) + return ret; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + ret = max17085_bat_get_volt(psy, val); + if (ret) + return ret; + break; + case POWER_SUPPLY_PROP_MANUFACTURER: + ret = max17085_bat_get_mfr(psy, val); + if (ret) + return ret; + break; + case POWER_SUPPLY_PROP_TECHNOLOGY: + ret = max17085_bat_get_tech(psy, val); + if (ret) + return ret; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = 1; + break; + case POWER_SUPPLY_PROP_TEMP: + val->intval = MAX17085_DEF_TEMP; + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + +static int max17085_ac_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max17085_chip *chip = container_of(psy, + struct max17085_chip, ac); + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = chip->online; + break; + default: + break; + } + + return 0; +} + +static void max17085_get_online(struct max17085_chip *chip) +{ + int level = gpio_get_value(chip->ac_in); + int cur_online = !level; + + if (chip->online != cur_online) { + chip->online = cur_online; + power_supply_changed(&chip->ac); + } +} + +static void max17085_get_health(struct max17085_chip *chip) +{ + int level = gpio_get_value(chip->pwr_good); + + if (level && (chip->voltage_uV >= 0)) + chip->health = POWER_SUPPLY_HEALTH_GOOD; + else + chip->health = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; +} + +extern int da9052_adc_read(unsigned char channel); +#define VOLT_REG_TO_MV(val) ((val * 2500) / 1024) +#define BATT_TO_ADC_SCALE 11 +#define DA9052_ADCMAN_ADCIN6 6 +static void max17085_get_volt(struct max17085_chip *chip) +{ + int val; + val = da9052_adc_read(DA9052_ADCMAN_ADCIN6); + + /* Ignore lower 2 bits out of 10 bits due to noise */ + val = val & 0x3fc; + if (val > 0) + chip->voltage_uV = VOLT_REG_TO_MV(val)*1000*BATT_TO_ADC_SCALE; + else + chip->voltage_uV = -1; +} + +#define BATT_EMPTY_MV 9955 +#define BATT_FULL_MV 12000 +static void max17085_get_cap(struct max17085_chip *chip) +{ + int old_cap = chip->cap; + + if (chip->voltage_uV > BATT_EMPTY_MV*1000) { + chip->cap = (chip->voltage_uV/1000 - BATT_EMPTY_MV) * 100/ + (BATT_FULL_MV - BATT_EMPTY_MV); + if (chip->cap > 100) + chip->cap = 100; + } else + chip->cap = 0; + + if (chip->cap != old_cap) + power_supply_changed(&chip->bat); +} + +static void max17085_update_status(struct max17085_chip *chip) +{ + int old_status = chip->status; + + if (chip->online) { + if (chip->voltage_uV/1000 < BATT_FULL_MV) + chip->status = + POWER_SUPPLY_STATUS_CHARGING; + else + chip->status = + POWER_SUPPLY_STATUS_NOT_CHARGING; + } else + chip->status = POWER_SUPPLY_STATUS_DISCHARGING; + + if (chip->voltage_uV/1000 >= BATT_FULL_MV) + chip->status = POWER_SUPPLY_STATUS_FULL; + + if (old_status != POWER_SUPPLY_STATUS_UNKNOWN && + old_status != chip->status) + power_supply_changed(&chip->bat); + + if (chip->cap < 20) { + gpio_set_value(chip->charge_now, 1); + gpio_set_value(chip->charge_done, 0); + } else if (chip->cap < 80) { + gpio_set_value(chip->charge_now, 1); + gpio_set_value(chip->charge_done, 1); + } else { + gpio_set_value(chip->charge_now, 0); + gpio_set_value(chip->charge_done, 1); + } +} + +static void max17085_work(struct work_struct *work) +{ + struct max17085_chip *chip = container_of(work, + struct max17085_chip, work.work); + + max17085_get_online(chip); + max17085_get_volt(chip); + max17085_get_health(chip); + max17085_get_cap(chip); + max17085_update_status(chip); + + schedule_delayed_work(&chip->work, msecs_to_jiffies(MAX17085_DELAY)); +} + +static enum power_supply_property max17085_bat_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_MANUFACTURER, +}; + +static enum power_supply_property max17085_ac_props[] = { + POWER_SUPPLY_PROP_ONLINE, +}; + +static int max17085_bat_probe(struct platform_device *pdev) +{ + int ret = 0; + struct max17085_chip *chip; + struct resource *res; + + chip = kzalloc(sizeof(struct max17085_chip), GFP_KERNEL); + if (!chip) { + ret = -ENOMEM; + goto chip_alloc_failed; + } + + res = platform_get_resource_byname(pdev, + IORESOURCE_IO, "pwr-good"); + if (res == NULL) { + ret = -EINVAL; + goto resource_failed; + } + chip->pwr_good = res->start; + res = platform_get_resource_byname(pdev, + IORESOURCE_IO, "ac-in"); + if (res == NULL) { + ret = -EINVAL; + goto resource_failed; + } + chip->ac_in = res->start; + res = platform_get_resource_byname(pdev, + IORESOURCE_IO, "charge-now"); + if (res == NULL) { + ret = -EINVAL; + goto resource_failed; + } + chip->charge_now = res->start; + res = platform_get_resource_byname(pdev, + IORESOURCE_IO, "charge-done"); + if (res == NULL) { + ret = -EINVAL; + goto resource_failed; + } + chip->charge_done = res->start; + + chip->dev = &pdev->dev; + chip->bat.name = "battery"; + chip->bat.type = POWER_SUPPLY_TYPE_BATTERY; + chip->bat.properties = max17085_bat_props; + chip->bat.num_properties = ARRAY_SIZE(max17085_bat_props); + chip->bat.get_property = max17085_bat_get_property; + chip->bat.use_for_apm = 1; + + chip->ac.name = "ac"; + chip->ac.type = POWER_SUPPLY_TYPE_MAINS; + chip->ac.properties = max17085_ac_props; + chip->ac.num_properties = ARRAY_SIZE(max17085_ac_props); + chip->ac.get_property = max17085_ac_get_property; + + platform_set_drvdata(pdev, chip); + + ret = power_supply_register(&pdev->dev, &chip->ac); + if (ret) { + dev_err(chip->dev, "failed to register ac\n"); + goto register_ac_failed; + } + + ret = power_supply_register(&pdev->dev, &chip->bat); + if (ret) { + dev_err(chip->dev, "failed to register battery\n"); + goto register_batt_failed; + } + + max17085_get_online(chip); + + INIT_DELAYED_WORK_DEFERRABLE(&chip->work, max17085_work); + schedule_delayed_work(&chip->work, msecs_to_jiffies(MAX17085_DELAY)); + + return ret; + +register_batt_failed: + power_supply_unregister(&chip->ac); +register_ac_failed: +resource_failed: + kfree(chip); +chip_alloc_failed: + return ret; +} + +static int max17085_bat_remove(struct platform_device *pdev) +{ + struct max17085_chip *chip = platform_get_drvdata(pdev); + + cancel_delayed_work(&chip->work); + power_supply_unregister(&chip->bat); + power_supply_unregister(&chip->ac); + kfree(chip); + + return 0; +} + +static void max17085_bat_shutdown(struct platform_device *pdev) +{ + struct max17085_chip *chip = platform_get_drvdata(pdev); + + cancel_delayed_work_sync(&chip->work); + gpio_set_value(chip->charge_now, 0); + gpio_set_value(chip->charge_done, 0); +} + +static struct platform_driver max17085_bat_driver = { + .probe = max17085_bat_probe, + .remove = max17085_bat_remove, + .shutdown = max17085_bat_shutdown, + .driver = { + .name = "max17085_bat", + }, + +}; + +static int __devinit max17085_bat_init(void) +{ + return platform_driver_register(&max17085_bat_driver); +} + +static void __devexit max17085_bat_exit(void) +{ + platform_driver_unregister(&max17085_bat_driver); +} + +module_init(max17085_bat_init); +module_exit(max17085_bat_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MAX17085 battery driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 0a6deb268b38..f28959ef9ab7 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -777,7 +777,7 @@ static void print_constraints(struct regulator_dev *rdev) if (constraints->valid_modes_mask & REGULATOR_MODE_STANDBY) count += sprintf(buf + count, "standby"); - rdev_info(rdev, "%s\n", buf); + rdev_dbg(rdev, "%s\n", buf); } static int machine_constraints_voltage(struct regulator_dev *rdev, @@ -1159,6 +1159,12 @@ static struct regulator *_regulator_get(struct device *dev, const char *id, } } + list_for_each_entry(rdev, ®ulator_list, list) { + if (strcmp(rdev->desc->name, id) == 0) { + goto found; + } + } + if (board_wants_dummy_regulator) { rdev = dummy_regulator_rdev; goto found; diff --git a/drivers/regulator/da9052-regulator.c b/drivers/regulator/da9052-regulator.c index 09882ddd8d92..0ec4666f977d 100755 --- a/drivers/regulator/da9052-regulator.c +++ b/drivers/regulator/da9052-regulator.c @@ -142,12 +142,12 @@ struct regulator_info da9052_regulators[] = { DA9052_BUCK_MEM_VOLT_LOWER, DA9052_BUCK_MEM_STEP, DA9052_BUCKMEM_REG, DA9052_BUCKMEM_VBMEM, DA9052_BUCKMEM_BMEMEN), -#if defined (CONFIG_PMIC_DA9052) +#if defined(CONFIG_PMIC_DA9052) DA9052_LDO(DA9052_BUCK_PERI, DA9052_BUCK_PERI_VOLT_UPPER, DA9052_BUCK_PERI_VOLT_LOWER, DA9052_BUCK_PERI_STEP_BELOW_3000, DA9052_BUCKPERI_REG, DA9052_BUCKPERI_VBPERI, DA9052_BUCKPERI_BPERIEN), -#elif defined (CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx) +#elif defined(CONFIG_PMIC_DA9053AA) || defined(CONFIG_PMIC_DA9053Bx) DA9052_LDO(DA9052_BUCK_PERI, DA9052_BUCK_PERI_VOLT_UPPER, DA9052_BUCK_PERI_VOLT_LOWER, DA9052_BUCK_PERI_STEP, DA9052_BUCKPERI_REG, @@ -247,7 +247,7 @@ int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev, int id = rdev_get_id(rdev); int ret; int ldo_volt = 0; - selector; + (void)selector; /* Below if condition is there for added setvoltage attribute in sysfs */ @@ -265,7 +265,7 @@ int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev, if (max_uV < da9052_regulators[id].reg_const.min_uV || max_uV > da9052_regulators[id].reg_const.max_uV) return -EINVAL; -#if defined (CONFIG_PMIC_DA9052) +#if defined(CONFIG_PMIC_DA9052) /* Get the ldo register value */ /* Varying step size for BUCK PERI */ if ((da9052_regulators[id].reg_desc.id == DA9052_BUCK_PERI) && @@ -283,7 +283,7 @@ int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev, da9052_regulators[id].reg_const.min_uV > max_uV) return -EINVAL; } -#elif defined (CONFIG_PMIC_DA9053AA) ||(CONFIG_PMIC_DA9053Bx) +#elif defined(CONFIG_PMIC_DA9053AA) || defined(CONFIG_PMIC_DA9053Bx) ldo_volt = (min_uV - da9052_regulators[id].reg_const.min_uV)/ (da9052_regulators[id].step_uV); /* Check for maximum value */ @@ -378,7 +378,7 @@ int da9052_ldo_buck_get_voltage(struct regulator_dev *rdev) da9052_unlock(priv->da9052); ldo_volt = ssc_msg.data & da9052_regulators[id].mask_bits; -#if defined (CONFIG_PMIC_DA9052) +#if defined(CONFIG_PMIC_DA9052) if (da9052_regulators[id].reg_desc.id == DA9052_BUCK_PERI) { if (ldo_volt >= DA9052_BUCK_PERI_VALUES_UPTO_3000) { ldo_volt_uV = ((DA9052_BUCK_PERI_VALUES_UPTO_3000 * @@ -396,7 +396,7 @@ int da9052_ldo_buck_get_voltage(struct regulator_dev *rdev) ldo_volt_uV = (ldo_volt * da9052_regulators[id].step_uV) + da9052_regulators[id].reg_const.min_uV; } -#elif defined (CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx) +#elif defined(CONFIG_PMIC_DA9053AA) || defined(CONFIG_PMIC_DA9053Bx) ldo_volt_uV = (ldo_volt * da9052_regulators[id].step_uV) + da9052_regulators[id].reg_const.min_uV; #endif diff --git a/drivers/regulator/mc13892-regulator.c b/drivers/regulator/mc13892-regulator.c index 04ce02869d9c..d052adff55c4 100644 --- a/drivers/regulator/mc13892-regulator.c +++ b/drivers/regulator/mc13892-regulator.c @@ -431,8 +431,7 @@ static int mc13892_sw_regulator_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV, unsigned *selector) { struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); - int hi, value, mask, id = rdev_get_id(rdev); - u32 valread; + int hi, value, val, mask, id = rdev_get_id(rdev); int ret; dev_dbg(rdev_get_dev(rdev), "%s id: %d min_uV: %d max_uV: %d\n", @@ -448,7 +447,7 @@ static int mc13892_sw_regulator_set_voltage(struct regulator_dev *rdev, mc13xxx_lock(priv->mc13xxx); ret = mc13xxx_reg_read(priv->mc13xxx, - mc13892_regulators[id].vsel_reg, &valread); + mc13892_regulators[id].vsel_reg, &val); if (ret) goto err; @@ -465,10 +464,8 @@ static int mc13892_sw_regulator_set_voltage(struct regulator_dev *rdev, value = (value - 600000) / 25000; mask = mc13892_regulators[id].vsel_mask | MC13892_SWITCHERS0_SWxHI; - valread = (valread & ~mask) | - (value << mc13892_regulators[id].vsel_shift); - ret = mc13xxx_reg_write(priv->mc13xxx, mc13892_regulators[id].vsel_reg, - valread); + ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].vsel_reg, + mask, value << mc13892_regulators[id].vsel_shift); err: mc13xxx_unlock(priv->mc13xxx); diff --git a/drivers/rtc/rtc-da9052.c b/drivers/rtc/rtc-da9052.c index 952a106ebb19..dd6bf53457b2 100755 --- a/drivers/rtc/rtc-da9052.c +++ b/drivers/rtc/rtc-da9052.c @@ -1,5 +1,6 @@ /* * Copyright(c) 2009 Dialog Semiconductor Ltd. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,13 +51,12 @@ void da9052_rtc_notifier(struct da9052_eh_nb *eh_data, unsigned int event) da9052_unlock(rtc->da9052); - if (msg.data & DA9052_ALARMMI_ALARMTYPE) { da9052_rtc_enable_alarm(rtc->da9052, 0); - printk(KERN_INFO "RTC: TIMER ALARM\n"); + pr_debug("RTC: TIMER ALARM\n"); } else { kobject_uevent(&rtc->rtc->dev.kobj, KOBJ_CHANGE); - printk(KERN_INFO "RTC: TICK ALARM\n"); + pr_debug("RTC: TICK ALARM\n"); } } @@ -261,8 +261,6 @@ static int da9052_alarm_settime(struct da9052 *da9052, struct rtc_time *rtc_tm) unsigned char loop_index = 0; int ret = 0; - rtc_tm->tm_sec = 0; - /* System compatability */ rtc_tm->tm_year -= 100; rtc_tm->tm_mon += 1; @@ -281,6 +279,24 @@ static int da9052_alarm_settime(struct da9052 *da9052, struct rtc_time *rtc_tm) return ret; } + /* Since DA9053 does support seconds timer, go to next mins boundary */ + if (rtc_tm->tm_sec) { + rtc_tm->tm_min = rtc_tm->tm_min + 1; + rtc_tm->tm_sec = 0; + + /* If minutes rolls over the boundary */ + if (rtc_tm->tm_min > 59) { + rtc_tm->tm_hour = rtc_tm->tm_hour + 1; + rtc_tm->tm_min = 0; + + /* If hours rolls over the boundary */ + if (rtc_tm->tm_hour > 23) { + rtc_tm->tm_mday = rtc_tm->tm_mday + 1; + rtc_tm->tm_hour = 0; + } + } + } + msg.data = msg.data & ~(DA9052_ALARMMI_ALARMMIN); msg.data |= rtc_tm->tm_min; @@ -309,9 +325,8 @@ static int da9052_alarm_settime(struct da9052 *da9052, struct rtc_time *rtc_tm) } msg.data = msg.data & ~(DA9052_ALARMY_ALARMYEAR); - - msg.data |= rtc_tm->tm_year; + msg_arr[loop_index].addr = DA9052_ALARMY_REG; msg_arr[loop_index].data = 0; msg_arr[loop_index++].data = msg.data; @@ -336,8 +351,8 @@ static int da9052_rtc_get_alarm_status(struct da9052 *da9052) da9052_lock(da9052); ret = da9052->read(da9052, &msg); if (ret != 0) { - da9052_unlock(da9052); - return ret; + da9052_unlock(da9052); + return ret; } da9052_unlock(da9052); @@ -370,45 +385,14 @@ static int da9052_rtc_enable_alarm(struct da9052 *da9052, unsigned char flag) da9052_unlock(da9052); return ret; } - da9052_unlock(da9052); - - return 0; -} - - -static ssize_t da9052_rtc_mask_irq(struct da9052 *da9052) - { - unsigned char data = 0; - ssize_t ret = 0; - struct da9052_ssc_msg ssc_msg; - - ssc_msg.addr = DA9052_IRQMASKA_REG; - ssc_msg.data = 0; - - da9052_lock(da9052); - ret = da9052->read(da9052, &ssc_msg); - if (ret != 0) { - da9052_unlock(da9052); - return ret; - } - - data = ret; - ssc_msg.data = data |= DA9052_IRQMASKA_MALRAM; - - ret = da9052->write(da9052, &ssc_msg); - if (ret != 0) { - da9052_unlock(da9052); - return ret; - } da9052_unlock(da9052); + return 0; } - static ssize_t da9052_rtc_unmask_irq(struct da9052 *da9052) { - unsigned char data = 0; ssize_t ret = 0; struct da9052_ssc_msg ssc_msg; @@ -422,8 +406,8 @@ static ssize_t da9052_rtc_unmask_irq(struct da9052 *da9052) return ret; } - data = ret; - ssc_msg.data = data &= ~DA9052_IRQMASKA_MALRAM; + ssc_msg.data &= ~DA9052_IRQMASKA_MALRAM; + ssc_msg.data |= DA9052_IRQMASKA_MSEQRDY; ret = da9052->write(da9052, &ssc_msg); if (ret != 0) { @@ -462,6 +446,7 @@ static int da9052_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) int ret; struct rtc_time *tm = &alrm->time; struct da9052 *da9052 = dev_get_drvdata(dev->parent); + ret = da9052_alarm_gettime(da9052, tm); if (ret) @@ -479,29 +464,19 @@ static int da9052_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) struct rtc_time *tm = &alrm->time; struct da9052 *da9052 = dev_get_drvdata(dev->parent); - ret = da9052_alarm_settime(da9052, tm); + ret = da9052_rtc_enable_alarm(da9052, 0); + if (ret) + return ret; + ret = da9052_alarm_settime(da9052, tm); if (ret) return ret; ret = da9052_rtc_enable_alarm(da9052, 1); + if (ret) + return ret; - return ret; -} - -static int da9052_rtc_update_irq_enable(struct device *dev, - unsigned int enabled) -{ - struct da9052_rtc *priv = dev_get_drvdata(dev); - int ret = -ENODATA; - - da9052_lock(priv->da9052); - - ret = (enabled ? da9052_rtc_unmask_irq : da9052_rtc_mask_irq) - (priv->da9052); - - da9052_unlock(priv->da9052); - + ret = da9052_rtc_unmask_irq(da9052); return ret; } @@ -510,10 +485,7 @@ static int da9052_rtc_alarm_irq_enable(struct device *dev, { struct da9052_rtc *priv = dev_get_drvdata(dev); - if (enabled) - return da9052_rtc_enable_alarm(priv->da9052, enabled); - else - return da9052_rtc_enable_alarm(priv->da9052, enabled); + return da9052_rtc_enable_alarm(priv->da9052, enabled); } static const struct rtc_class_ops da9052_rtc_ops = { @@ -521,10 +493,7 @@ static const struct rtc_class_ops da9052_rtc_ops = { .set_time = da9052_rtc_class_ops_settime, .read_alarm = da9052_rtc_readalarm, .set_alarm = da9052_rtc_setalarm, -#if 0 - .update_irq_enable = da9052_rtc_update_irq_enable, .alarm_irq_enable = da9052_rtc_alarm_irq_enable, -#endif }; @@ -553,7 +522,7 @@ static int __devinit da9052_rtc_probe(struct platform_device *pdev) goto err_register_alarm; priv->is_min_alarm = 1; - priv->enable_tick_alarm = 1; + priv->enable_tick_alarm = 0; priv->enable_clk_buffer = 1; priv->set_osc_trim_freq = 5; /* Enable/Disable TICK Alarm */ @@ -635,6 +604,8 @@ static int __devinit da9052_rtc_probe(struct platform_device *pdev) goto err_ssc_comm; } da9052_unlock(priv->da9052); + /* disable rtc-alarm */ + da9052_rtc_enable_alarm(priv->da9052, 0); priv->rtc = rtc_device_register(pdev->name, &pdev->dev, &da9052_rtc_ops, THIS_MODULE); diff --git a/drivers/rtc/rtc-mc34708.c b/drivers/rtc/rtc-mc34708.c index 31e58f9e9cff..d67d4f8330c1 100644 --- a/drivers/rtc/rtc-mc34708.c +++ b/drivers/rtc/rtc-mc34708.c @@ -306,12 +306,6 @@ static irqreturn_t mc34708_rtc_update_handler(int irq, void *dev) } static int -mc34708_rtc_update_irq_enable(struct device *dev, unsigned int enabled) -{ - return mc34708_rtc_irq_enable(dev, enabled, MC_PMIC_IRQ_1HZ); -} - -static int mc34708_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) { return mc34708_rtc_irq_enable(dev, enabled, MC_PMIC_IRQ_TODA); @@ -323,7 +317,6 @@ static const struct rtc_class_ops mc34708_rtc_ops = { .read_alarm = mc34708_rtc_read_alarm, .set_alarm = mc34708_rtc_set_alarm, .alarm_irq_enable = mc34708_rtc_alarm_irq_enable, - .update_irq_enable = mc34708_rtc_update_irq_enable, }; static irqreturn_t mc34708_rtc_reset_handler(int irq, void *dev) diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index d65c589cef60..06f8e258dd38 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -1767,6 +1767,7 @@ static int __init imx_serial_init(void) if (ret != 0) uart_unregister_driver(&imx_reg); + printk(KERN_INFO "Serial: IMX driver done\n"); return 0; } diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c index 493abd662036..0c89d1ab0b30 100644 --- a/drivers/video/mxc/ldb.c +++ b/drivers/video/mxc/ldb.c @@ -216,7 +216,7 @@ static int find_ldb_setting(struct ldb_data *ldb, struct fb_info *fbi) static int ldb_disp_setup(struct mxc_dispdrv_handle *disp, struct fb_info *fbi) { uint32_t reg, val; - uint32_t pixel_clk, rounded_pixel_clk; + uint32_t pixel_clk, rounded_pixel_clk, pixel_clk_roundup, pixel_clk_rounddown; struct clk *ldb_clk_parent; struct ldb_data *ldb = mxc_dispdrv_getdata(disp); int setting_idx, di; @@ -254,7 +254,18 @@ static int ldb_disp_setup(struct mxc_dispdrv_handle *disp, struct fb_info *fbi) /* clk setup */ if (ldb->setting[setting_idx].clk_en) clk_disable(ldb->setting[setting_idx].ldb_di_clk); - pixel_clk = (PICOS2KHZ(fbi->var.pixclock)) * 1000UL; + pixel_clk = (PICOS2KHZ(fbi->var.pixclock)); + /* Round Pixel Clk to next MHz */ + pixel_clk_roundup = roundup(pixel_clk,1000); + /* Round Pixel Clk to down MHz */ + pixel_clk_rounddown = rounddown(pixel_clk,1000); + /* Choose the one closest */ + if ((pixel_clk_roundup - pixel_clk) > (pixel_clk - pixel_clk_rounddown)) + pixel_clk = pixel_clk_rounddown; + else + pixel_clk = pixel_clk_roundup; + + pixel_clk *= 1000UL; ldb_clk_parent = clk_get_parent(ldb->setting[setting_idx].ldb_di_clk); if ((ldb->mode == LDB_SPL_DI0) || (ldb->mode == LDB_SPL_DI1)) clk_set_rate(ldb_clk_parent, pixel_clk * 7 / 2); diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c index a087f3323233..ab069152e57c 100644 --- a/drivers/video/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -94,6 +94,9 @@ struct mxcfb_info { struct fb_info *ovfbi; struct mxc_dispdrv_handle *dispdrv; + bool fb_suspended; + int panel_width_mm; + int panel_height_mm; }; struct mxcfb_alloc_list { @@ -388,7 +391,8 @@ static int mxcfb_set_par(struct fb_info *fbi) } } - if (mxc_fbi->next_blank != FB_BLANK_UNBLANK) + if (mxc_fbi->next_blank != FB_BLANK_UNBLANK || + mxc_fbi->fb_suspended) return retval; _setup_disp_channel1(fbi); @@ -745,8 +749,16 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) var->pixclock); } - var->height = -1; - var->width = -1; + if (mxc_fbi->panel_height_mm) + var->height = mxc_fbi->panel_height_mm; + else + var->height = -1; + + if (mxc_fbi->panel_width_mm) + var->width = mxc_fbi->panel_width_mm; + else + var->width = -1; + var->grayscale = 0; return 0; @@ -1195,6 +1207,9 @@ static int mxcfb_blank(int blank, struct fb_info *info) dev_dbg(info->device, "blank = %d\n", blank); + if (mxc_fbi->fb_suspended) + return -EAGAIN; + if (mxc_fbi->cur_blank == blank) return 0; @@ -1524,6 +1539,7 @@ static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state) saved_blank = mxc_fbi->cur_blank; mxcfb_blank(FB_BLANK_POWERDOWN, fbi); mxc_fbi->next_blank = saved_blank; + mxc_fbi->fb_suspended = true; console_unlock(); return 0; @@ -1538,6 +1554,7 @@ static int mxcfb_resume(struct platform_device *pdev) struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; console_lock(); + mxc_fbi->fb_suspended = false; mxcfb_blank(mxc_fbi->next_blank, fbi); fb_set_suspend(fbi, 0); console_unlock(); @@ -2047,7 +2064,11 @@ static int mxcfb_probe(struct platform_device *pdev) mxcfb_option_setup(pdev); mxcfbi = (struct mxcfb_info *)fbi->par; + mxcfbi->fb_suspended = false; mxcfbi->ipu_int_clk = plat_data->int_clk; + mxcfbi->panel_width_mm = plat_data->panel_width_mm; + mxcfbi->panel_height_mm = plat_data->panel_height_mm; + ret = mxcfb_dispdrv_init(pdev, fbi); if (ret < 0) goto init_dispdrv_failed; diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c index ad2a40fefc6c..249a66eb6611 100644 --- a/drivers/watchdog/imx2_wdt.c +++ b/drivers/watchdog/imx2_wdt.c @@ -2,6 +2,7 @@ * Watchdog driver for IMX2 and later processors * * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de> + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * some parts adapted by similar drivers from Darius Augulis and Vladimir * Zapolskiy, additional improvements by Wim Van Sebroeck. @@ -41,6 +42,7 @@ #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */ #define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */ #define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */ +#define IMX2_WDT_WCR_WDBG (1 << 1) /* -> Watchdog DBG bit */ #define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */ #define IMX2_WDT_WSR 0x02 /* Service Register */ @@ -88,6 +90,8 @@ static inline void imx2_wdt_setup(void) /* Suspend watch dog timer in low power mode, write once-only */ val |= IMX2_WDT_WCR_WDZST; + /* Enable Watchdog Debug */ + val |= IMX2_WDT_WCR_WDBG; /* Strip the old watchdog Time-Out value */ val &= ~IMX2_WDT_WCR_WT; /* Generate reset if WDOG times out */ diff --git a/firmware/imx/sdma/sdma-imx53-to1.bin.ihex b/firmware/imx/sdma/sdma-imx53-to1.bin.ihex index 4b3c996dbcd7..c29ef927877e 100644 --- a/firmware/imx/sdma/sdma-imx53-to1.bin.ihex +++ b/firmware/imx/sdma/sdma-imx53-to1.bin.ihex @@ -1,89 +1,90 @@ -:1000000053444D4101000000000000001C000000AE -:1000100023000000A8000000D604000082020000B7 +:1000000053444D4101000000010000001C000000AD +:1000100025000000B0000000D604000082020000AD :10002000FFFFFFFF00000000FFFFFFFFFFFFFFFFDC :10003000FFFFFFFFFFFFFFFFA9040000FFFFFFFF1F -:10004000F6FAFFFFFFFFFFFF31030000FFFFFFFF96 +:100040000A050000FFFFFFFF31030000FFFFFFFF75 :10005000EB020000BB180000FFFFFFFF08040000D8 :10006000FFFFFFFFC0030000FFFFFFFFFFFFFFFFD9 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+:10053000011F03200048EA7CE3555E9A1500150070 +:100540001500047806520B6A26520B6A5D9A150054 +:100550001500047806520A6A26520A6A5D9A150046 +:1005600004780652096A2652096A097C286A077FBC +:100570000000DB57004D057DFAC1DB571C9A77C29E +:0605800054040AC2199A9E :00000001FF diff --git a/include/linux/i2c/mpr.h b/include/linux/i2c/mpr.h index ded00db775f3..8dbbee648098 100644 --- a/include/linux/i2c/mpr.h +++ b/include/linux/i2c/mpr.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -43,6 +43,7 @@ * should be write at last. */ #define ELECTRODE_CONF_ADDR 0x5e +#define ECR_CL_BT_5BIT_VAL 0x80 #define AUTO_CONFIG_CTRL_ADDR 0x7b /* AUTO_CONFIG_USL: Upper Limit for auto baseline search, this * register is related to VDD supplied on your board, the value of @@ -55,7 +56,7 @@ #define AUTO_CONFIG_TL_ADDR 0x7f /* Threshold of touch/release trigger */ -#define TOUCH_THRESHOLD 0x0f +#define TOUCH_THRESHOLD 0x0c #define RELEASE_THRESHOLD 0x0a /* Mask Button bits of STATUS_0 & STATUS_1 register */ #define TOUCH_STATUS_MASK 0xfff diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h index fd83f73bcd82..18dd74bde4f8 100755 --- a/include/linux/mfd/da9052/da9052.h +++ b/include/linux/mfd/da9052/da9052.h @@ -75,6 +75,9 @@ #define DA9052_SSC_I2C_REPEAT_WRITE_MODE 1 #define DA9052_SSC_I2C_WRITE_MODE DA9052_SSC_I2C_REPEAT_WRITE_MODE +#define DA9053_VERSION_AA 1 +#define DA9053_VERSION_BB 2 + struct da9052_ssc_msg { unsigned char data; unsigned char addr; @@ -95,7 +98,6 @@ struct da9052_eh_nb{ struct da9052_regulator_init_data { struct regulator_init_data *init_data; int id; - }; struct da9052_regulator_platform_data { @@ -114,6 +116,25 @@ struct da9052_tsi_platform_data { }; +struct da9052_bat_platform_data { + u16 sw_temp_control_en; + u16 monitoring_interval; + u16 sw_bat_temp_threshold; + u16 sw_junc_temp_threshold; + u16 hysteresis_window_size; + u16 current_monitoring_window; + u16 bat_with_no_resistor; + u16 bat_capacity_limit_low; + u16 bat_capacity_full; + u16 bat_capacity_limit_high; + u16 chg_hysteresis_const; + u16 hysteresis_reading_interval; + u16 hysteresis_no_of_reading; + u16 filter_size; + u16 bat_volt_cutoff; + u16 vbat_first_valid_detect_iteration; +}; + struct da9052 { struct mutex ssc_lock; struct mutex eve_nb_lock; @@ -143,9 +164,9 @@ struct da9052 { struct device *dev; struct i2c_adapter *adapter; unsigned char slave_addr; + int chip_version; }; - struct da9052_platform_data { int (*init)(struct da9052 *da9052); int irq_high; @@ -156,6 +177,7 @@ struct da9052_platform_data { struct regulator_init_data *regulators; struct da9052_leds_platform_data *led_data; struct da9052_tsi_platform_data *tsi_data; + struct da9052_bat_platform_data *bat_data; }; struct da9052_ssc_ops { @@ -206,4 +228,6 @@ int eh_register_nb(struct da9052 *da9052, struct da9052_eh_nb *nb); int eh_unregister_nb(struct da9052 *da9052, struct da9052_eh_nb *nb); int da9052_manual_read(struct da9052 *da9052, unsigned char channel); +void da9053_power_off(void); +int da9053_get_chip_version(void); #endif /* __LINUX_MFD_DA9052_DA9052_H */ diff --git a/include/linux/mfd/da9052/pm.h b/include/linux/mfd/da9052/pm.h index 9a1c4f8b4ea8..f5901e8f1ed1 100644 --- a/include/linux/mfd/da9052/pm.h +++ b/include/linux/mfd/da9052/pm.h @@ -50,14 +50,14 @@ #define DA9052_BUCK_MEM_VOLT_UPPER 2500 #define DA9052_BUCK_MEM_VOLT_LOWER 925 #define DA9052_BUCK_MEM_STEP 25 -#if defined (CONFIG_PMIC_DA9052) +#if defined(CONFIG_PMIC_DA9052) #define DA9052_BUCK_PERI_VOLT_UPPER 3600 #define DA9052_BUCK_PERI_VOLT_LOWER 1800 #define DA9052_BUCK_PERI_STEP_BELOW_3000 50 #define DA9052_BUCK_PERI_STEP_ABOVE_3000 100000 #define DA9052_BUCK_PERI_VALUES_UPTO_3000 24 #define DA9052_BUCK_PERI_VALUES_3000 3000000 -#elif defined (CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx) +#elif defined(CONFIG_PMIC_DA9053AA) || defined(CONFIG_PMIC_DA9053Bx) #define DA9052_BUCK_PERI_VOLT_UPPER 2500 #define DA9052_BUCK_PERI_VOLT_LOWER 925 #define DA9052_BUCK_PERI_STEP 25 diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h index 9daaa02e565f..8c4c9dff8fe5 100644 --- a/include/linux/mfd/da9052/reg.h +++ b/include/linux/mfd/da9052/reg.h @@ -533,10 +533,10 @@ /* BUCKPERI REGISTER */ #define DA9052_BUCKPERI_BPERICONF (1<<7) #define DA9052_BUCKPERI_BPERIEN (1<<6) -#if defined (CONFIG_PMIC_DA9052) +#if defined(CONFIG_PMIC_DA9052) #define DA9052_BUCKPERI_BPERIHS (1<<5) #define DA9052_BUCKPERI_VBPERI (31<<0) -#elif defined (CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx) +#elif defined(CONFIG_PMIC_DA9053AA) || defined(CONFIG_PMIC_DA9053Bx) #define DA9052_BUCKPERI_VBPERI (63<<0) #endif @@ -663,7 +663,7 @@ #define DA9052_BOOST_BOOSTEN (1<<0) /* LED COUNT REGISTER */ -#if defined (CONFIG_PMIC_DA9053Bx) +#if defined(CONFIG_PMIC_DA9053Bx) #define DA9052_LEDCONT_SELLEDMODE (1<<7) #endif #define DA9052_LEDCONT_LED3ICONT (1<<6) diff --git a/include/linux/rfkill.h b/include/linux/rfkill.h index c6c608482cba..08c32e4f261a 100644 --- a/include/linux/rfkill.h +++ b/include/linux/rfkill.h @@ -354,6 +354,37 @@ static inline bool rfkill_blocked(struct rfkill *rfkill) } #endif /* RFKILL || RFKILL_MODULE */ + +#ifdef CONFIG_RFKILL_LEDS +/** + * rfkill_get_led_trigger_name - Get the LED trigger name for the button's LED. + * This function might return a NULL pointer if registering of the + * LED trigger failed. Use this as "default_trigger" for the LED. + */ +const char *rfkill_get_led_trigger_name(struct rfkill *rfkill); + +/** + * rfkill_set_led_trigger_name -- set the LED trigger name + * @rfkill: rfkill struct + * @name: LED trigger name + * + * This function sets the LED trigger name of the radio LED + * trigger that rfkill creates. It is optional, but if called + * must be called before rfkill_register() to be effective. + */ +void rfkill_set_led_trigger_name(struct rfkill *rfkill, const char *name); +#else +static inline const char *rfkill_get_led_trigger_name(struct rfkill *rfkill) +{ + return NULL; +} + +static inline void +rfkill_set_led_trigger_name(struct rfkill *rfkill, const char *name) +{ +} +#endif + #endif /* __KERNEL__ */ #endif /* RFKILL_H */ diff --git a/sound/soc/codecs/mxc_spdif.c b/sound/soc/codecs/mxc_spdif.c index 2bcb4d68274b..f190c4540b95 100644 --- a/sound/soc/codecs/mxc_spdif.c +++ b/sound/soc/codecs/mxc_spdif.c @@ -33,6 +33,7 @@ #include <sound/soc-dapm.h> #include <sound/initval.h> #include <mach/hardware.h> +#include <mach/clock.h> #include "mxc_spdif.h" @@ -74,6 +75,7 @@ struct mxc_spdif_priv { atomic_t dpll_locked; /* DPLL locked status */ bool tx_active; bool rx_active; + int resume_core_clk; }; struct spdif_mixer_control mxc_spdif_control; @@ -1140,15 +1142,20 @@ static int mxc_spdif_soc_suspend(struct snd_soc_codec *codec, plat_data = spdif_priv->plat_data; - if (spdif_priv->tx_active) { - clk_disable(plat_data->spdif_audio_clk); - clk_disable(plat_data->spdif_clk); - } + if (clk_get_usecount(plat_data->spdif_core_clk)) { + if (spdif_priv->tx_active) { + clk_disable(plat_data->spdif_audio_clk); + clk_disable(plat_data->spdif_clk); + } - if (spdif_priv->rx_active) - clk_disable(plat_data->spdif_clk); + if (spdif_priv->rx_active) + clk_disable(plat_data->spdif_clk); - clk_disable(plat_data->spdif_core_clk); + clk_disable(plat_data->spdif_core_clk); + spdif_priv->resume_core_clk = 1; + } + else + spdif_priv->resume_core_clk = 0; return 0; } @@ -1163,17 +1170,19 @@ static int mxc_spdif_soc_resume(struct snd_soc_codec *codec) plat_data = spdif_priv->plat_data; - clk_enable(plat_data->spdif_core_clk); + if (spdif_priv->resume_core_clk == 1) { + clk_enable(plat_data->spdif_core_clk); - if (spdif_priv->tx_active) { - clk_enable(plat_data->spdif_clk); - clk_enable(plat_data->spdif_audio_clk); - } + if (spdif_priv->tx_active) { + clk_enable(plat_data->spdif_clk); + clk_enable(plat_data->spdif_audio_clk); + } - if (spdif_priv->rx_active) - clk_enable(plat_data->spdif_clk); + if (spdif_priv->rx_active) + clk_enable(plat_data->spdif_clk); - spdif_softreset(); + spdif_softreset(); + } return 0; } @@ -1236,6 +1245,7 @@ static int __devinit mxc_spdif_probe(struct platform_device *pdev) spdif_priv->tx_active = false; spdif_priv->rx_active = false; + spdif_priv->resume_core_clk = 0; platform_set_drvdata(pdev, spdif_priv); spdif_priv->reg_phys_base = res->start; diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig index b9f08b52bd1d..3cf8fe55aa06 100644 --- a/sound/soc/imx/Kconfig +++ b/sound/soc/imx/Kconfig @@ -53,7 +53,7 @@ config SND_SOC_PHYCORE_AC97 config SND_SOC_IMX_SGTL5000 tristate "SoC Audio support for i.MX boards with sgtl5000" depends on I2C && (MACH_MX35_3DS || MACH_MX51_BABBAGE \ - || MACH_MX6Q_SABRELITE || MACH_MX6Q_ARM2) + || MACH_MX53_SMD || MACH_MX6Q_SABRELITE || MACH_MX6Q_ARM2) select SND_SOC_SGTL5000 select SND_MXC_SOC_MX2 help @@ -79,7 +79,7 @@ config SND_SOC_IMX_WM8962 config SND_SOC_IMX_CS42888 tristate "SoC Audio support for i.MX boards with cs42888" - depends on I2C && (MACH_MX6Q_ARM2 || MACH_MX6Q_SABREAUTO || MACH_MX53_ARD) + depends on I2C && (MACH_MX6Q_ARM2 || MACH_MX6Q_SABREAUTO || MACH_MX53_ARD || MACH_MX53_SMD) select SND_SOC_CS42888 select SND_MXC_SOC_MX2 help diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/imx/imx-pcm.h index be0d5ffbe5d1..274af8ff7dcc 100644 --- a/sound/soc/imx/imx-pcm.h +++ b/sound/soc/imx/imx-pcm.h @@ -42,8 +42,6 @@ #include <mach/dma.h> -#include "imx-ssi.h" - struct imx_pcm_runtime_data { int period_bytes; int periods; diff --git a/sound/soc/imx/imx-sgtl5000.c b/sound/soc/imx/imx-sgtl5000.c index 9325dc8e346c..49c2934a44b9 100644 --- a/sound/soc/imx/imx-sgtl5000.c +++ b/sound/soc/imx/imx-sgtl5000.c @@ -3,7 +3,7 @@ * sgtl5000 codec * * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -43,7 +43,12 @@ static struct snd_soc_jack_pin hs_jack_pins[] = { .pin = "Headphone Jack", .mask = SND_JACK_HEADPHONE, }, -}; + { + .pin = "Ext Spk", + .mask = SND_JACK_HEADPHONE, + .invert = 1, + }, + }; /* Headphones jack detection gpios */ static struct snd_soc_jack_gpio hs_jack_gpios[] = { @@ -195,11 +200,29 @@ static int sgtl5000_set_line_in(struct snd_kcontrol *kcontrol, return 1; } +static int spk_amp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct imx_sgtl5000_priv *priv = &card_priv; + struct platform_device *pdev = priv->pdev; + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + + if (plat->amp_enable == NULL) + return 0; + + if (SND_SOC_DAPM_EVENT_ON(event)) + plat->amp_enable(1); + else + plat->amp_enable(0); + + return 0; +} + /* imx_3stack card dapm widgets */ static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = { SND_SOC_DAPM_MIC("Mic Jack", NULL), SND_SOC_DAPM_LINE("Line In Jack", NULL), - SND_SOC_DAPM_SPK("Ext Spk", NULL), + SND_SOC_DAPM_SPK("Ext Spk", spk_amp_event), SND_SOC_DAPM_HP("Headphone Jack", NULL), }; @@ -246,7 +269,8 @@ static int imx_3stack_sgtl5000_init(struct snd_soc_pcm_runtime *rtd) snd_soc_dapm_add_routes(&codec->dapm, audio_map, ARRAY_SIZE(audio_map)); snd_soc_dapm_disable_pin(&codec->dapm, "Line In Jack"); - snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack"); + snd_soc_dapm_disable_pin(&codec->dapm, "Headphone Jack"); + snd_soc_dapm_enable_pin(&codec->dapm, "Ext Spk"); snd_soc_dapm_sync(&codec->dapm); if (hs_jack_gpios[0].gpio != -1) { |