diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2021-10-27 11:31:16 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2021-10-27 11:31:16 +0200 |
| commit | b7164aa99f53059ce080dedc581f6fb9b3ce4d4f (patch) | |
| tree | a4eec42cc624140ef73c98568b5273da8c6dcb18 | |
| parent | c99d3f9d208ba0a127d401ba50a2e7f6340da7e1 (diff) | |
arm64: dts: imx8mm-verdin: fix pcie functionality
This fixes the following PCIe issue reported at boot-up:
[ 2.330528] imx6q-pcie 33800000.pcie: PCIe PLL lock timeout
Fixes: 3eff23ff4c9b
("MLK-25333-2 clk: imx8mm: remove the parent setting in clock driver")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index c7c072271ca8..b6f398cd5c2f 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -639,6 +639,13 @@ /* Verdin PCIE_1 */ &pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>, @@ -646,6 +653,7 @@ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; epdev_on-supply = <®_3p3v>; ext_osc = <0>; + l1ss-disabled; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reserved-region = <&rpmsg_reserved>; |