diff options
| author | Peng Fan <peng.fan@nxp.com> | 2020-03-22 15:30:44 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-04-09 10:35:39 +0800 |
| commit | b96f149d2f0e5372d0d20d45ff18d3e0fd3a91a6 (patch) | |
| tree | f20133c38ef8c87f79b2afa4e3fadd5d35f5ff5a | |
| parent | 189e62437de43a4721343d092c1015c07b39053c (diff) | |
MLK-23754-9 reset: imx7: add the M4 core reset for i.MX8MQ
Add the M4 core reset for i.MX8MQ, then we could use reset API
to start/stop M4.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | drivers/reset/reset-imx7.c | 4 | ||||
| -rw-r--r-- | include/dt-bindings/reset/imx8mq-reset.h | 5 |
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 57dad8263335..9fd73a98543c 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -165,6 +165,9 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) }, + [IMX8MQ_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, + [IMX8MQ_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, + [IMX8MQ_RESET_M4_ENABLE] = { SRC_M4RCR, BIT(3) }, [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, @@ -229,6 +232,7 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev, case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ + case IMX8MQ_RESET_M4_ENABLE: value = assert ? 0 : bit; break; } diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 2a04e9cffde1..47cc7f086cc6 100644 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -60,7 +60,10 @@ #define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ #define IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ 50 /* i.MX8M PCIe CTL CLK REQ */ #define IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ 51 /* i.MX8M PCIe CTL CLK REQ */ +#define IMX8MQ_RESET_SW_M4C_RST 52 +#define IMX8MQ_RESET_SW_M4P_RST 53 +#define IMX8MQ_RESET_M4_ENABLE 54 -#define IMX8MQ_RESET_NUM 52 +#define IMX8MQ_RESET_NUM 55 #endif |