diff options
| author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2014-10-07 12:13:49 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2014-10-07 12:13:49 -0500 |
| commit | c56e993f168b84b92ee4bd204b895b349e1397f9 (patch) | |
| tree | fe12b7632e260a91e57c581afd83cb375e5f754a | |
| parent | 31eaa38427340fb50249d861b1cd3bce0ca18c8b (diff) | |
MLK-9664 [imx6x] Remove unused commented code
Remove dead code.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/mx6_ddr_freq.S | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/arm/mach-mx6/mx6_ddr_freq.S b/arch/arm/mach-mx6/mx6_ddr_freq.S index 4705207a3fee..101e270ea370 100644 --- a/arch/arm/mach-mx6/mx6_ddr_freq.S +++ b/arch/arm/mach-mx6/mx6_ddr_freq.S @@ -506,32 +506,6 @@ wait_for_l2_to_idle: ldr r6, =0x0 mcr p15, 0, r6, c8, c3, 0 -#if RANJANI - /* Disable L1 data cache. */ - mrc p15, 0, r6, c1, c0, 0 - bic r6, r6, #0x4 - mcr p15, 0, r6, c1, c0, 0 - - dsb - -#ifdef CONFIG_CACHE_L2X0 - /* - * Sync L2 and then disable it. - */ - ldr r7, =L2_BASE_ADDR - add r7, r7, #PERIPBASE_VIRT - /* Wait for background operations to complete. */ -wait_for_l2_to_idle: - ldr r6, [r7, #0x730] - cmp r6, #0x0 - bne wait_for_l2_to_idle - ldr r6, =0x0 - str r6, [r7, #0x730] - /* Disable L2. */ - str r6, [r7, #0x100] -#endif -#endif - dsb isb |