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authorDong Aisheng <aisheng.dong@nxp.com>2019-07-19 14:46:36 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:05:06 +0800
commitd5bdd2aae9308a8fc8f5d0ecf89a708b18bf2a61 (patch)
tree428229803017319de4722a190b103efcbd9f970d
parent042f030b9014fc694f9e6352865febb4c6e22716 (diff)
arm64: dts: imx8qxp-enet2-tja1100: fix enet 50M ref clock
It's actually SCU clk, not LPCG clk. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi
index dd363d61efb8..851f8eaa3f08 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi
@@ -21,7 +21,7 @@
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_RMII_REF_50MHZ_CLK>,
+ <&clk IMX_CONN_ENET1_RMII_REF_50MHZ_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;