diff options
| author | Abel Vesa <abel.vesa@nxp.com> | 2019-09-30 12:50:59 +0300 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:27 +0800 |
| commit | dcddc1f4284832fb45a21e292860e9f7698572d2 (patch) | |
| tree | 04e2006c3cf9c18eae8174f3d259d7becfcab28c | |
| parent | fe3039b86d586c0f316ce758c1b9c91dd6b44b9c (diff) | |
clk: imx8qxp: Add JPEG encode/decode clocks
Clocks needed by JPEG Encoder/Decoder Linux V4L2 driver.
These additions are based on linux-imx/imx_4.19.y.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
(cherry picked from commit 7ac4b9c761b133cfb364d269d7e64db57c4863d8)
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi index ba3dbfe737d9..7faf3fe48fd8 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -200,34 +200,28 @@ img_subsys: bus@58000000 { power-domains = <&pd IMX_SC_R_CSI_1>; }; - img_jpeg_dec_lpcg: clock-controller@585d0000 { + img_jpeg_dec_clk: clock-controller@585d0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x585d0000 0x10000>; #clock-cells = <1>; clocks = <&img_ipg_clk>, <&img_ipg_clk>; - clock-indices = <IMX_LPCG_CLK_0>, - <IMX_LPCG_CLK_4>; - clock-output-names = "img_jpeg_dec_lpcg_clk", - "img_jpeg_dec_lpcg_ipg_clk"; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_dec_clk", + "img_jpeg_dec_ipg_clk"; power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; }; - img_jpeg_enc_lpcg: clock-controller@585f0000 { + img_jpeg_enc_clk: clock-controller@585f0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x585f0000 0x10000>; #clock-cells = <1>; clocks = <&img_ipg_clk>, <&img_ipg_clk>; - clock-indices = <IMX_LPCG_CLK_0>, - <IMX_LPCG_CLK_4>; - clock-output-names = "img_jpeg_enc_lpcg_clk", - "img_jpeg_enc_lpcg_ipg_clk"; + bit-offset = <0 16>; + clock-output-names = "img_jpeg_enc_clk", + "img_jpeg_enc_ipg_clk"; power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; }; - img_lpcg: clock-controller@58500000 { - compatible = "fsl,imx8qxp-lpcg-img"; - reg = <0x58500000 0xb0000>; - irqsteer_csi0: irqsteer@58220000 { compatible = "fsl,imx-irqsteer"; reg = <0x58220000 0x1000>; |