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authorAnson Huang <b20788@freescale.com>2011-08-02 17:22:56 +0800
committerJustin Waters <justin.waters@timesys.com>2012-07-03 16:54:00 -0400
commite732e7824bcc644084057f1ecdc7b173a947a90c (patch)
tree6daa585fd616b4f279bd3cd610318a8c73a22343
parent0f460aaf2bbea4b4b29a6887546a90344cd54f3e (diff)
ENGR00154056-1 [MX6]Enable dormant mode
Enable dormant mode on MX6, need to re-init gic and l2 cache, so we must remove the gic init and l2 cache init routine's __INIT section. Signed-off-by: Anson Huang <b20788@freescale.com>
-rw-r--r--arch/arm/common/gic.c2
-rw-r--r--arch/arm/mm/cache-l2x0.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 4ddd0a6ac7ff..e60138b88be9 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -350,7 +350,7 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
writel_relaxed(1, base + GIC_CPU_CTRL);
}
-void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
+void gic_init(unsigned int gic_nr, unsigned int irq_start,
void __iomem *dist_base, void __iomem *cpu_base)
{
struct gic_chip_data *gic;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 44c086710d2b..5891ea09d708 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -277,7 +277,7 @@ static void l2x0_disable(void)
spin_unlock_irqrestore(&l2x0_lock, flags);
}
-void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
__u32 aux;
__u32 cache_id;