diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-04-12 15:31:28 +0800 |
|---|---|---|
| committer | Liu Ying <victor.liu@nxp.com> | 2020-07-09 09:42:19 +0800 |
| commit | f9d0e0c46f1327fb217d7e1f42799ed7c5d02c01 (patch) | |
| tree | 64ae832f0f1ff73a71723e9c613abed6cf761eb7 | |
| parent | c30b395e8d940691440fd0b042c23af85298b8d7 (diff) | |
MLK-21509-2 gpu: imx: dpu: disengcfg: Add signature select support
This patch adds helper disengcfg_sig_select() support so that
users may select different taps(FrameGen, GammaCor, Matrix or
Dither) to do signature computation. Also, select FrameGen as
the default tap in _dpu_dec_init() and call it in dpu_dec_init().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
| -rw-r--r-- | drivers/gpu/imx/dpu/dpu-disengcfg.c | 18 | ||||
| -rw-r--r-- | include/video/dpu.h | 8 |
2 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/imx/dpu/dpu-disengcfg.c b/drivers/gpu/imx/dpu/dpu-disengcfg.c index 1885dbf4bec9..be7e8011c270 100644 --- a/drivers/gpu/imx/dpu/dpu-disengcfg.c +++ b/drivers/gpu/imx/dpu/dpu-disengcfg.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -31,6 +31,7 @@ typedef enum { #define POLEN_HIGH BIT(2) #define PIXINV_INV BIT(3) #define SRCSELECT 0x10 +#define SIG_SELECT_MASK 0x3 struct dpu_disengcfg { void __iomem *base; @@ -51,6 +52,19 @@ static inline void dpu_dec_write(struct dpu_disengcfg *dec, writel(value, dec->base + offset); } +void disengcfg_sig_select(struct dpu_disengcfg *dec, dec_sig_sel_t sig_sel) +{ + u32 val; + + mutex_lock(&dec->mutex); + val = dpu_dec_read(dec, SRCSELECT); + val &= ~SIG_SELECT_MASK; + val |= sig_sel; + dpu_dec_write(dec, SRCSELECT, val); + mutex_unlock(&dec->mutex); +} +EXPORT_SYMBOL_GPL(disengcfg_sig_select); + struct dpu_disengcfg *dpu_dec_get(struct dpu_soc *dpu, int id) { struct dpu_disengcfg *dec; @@ -115,6 +129,8 @@ void _dpu_dec_init(struct dpu_soc *dpu, unsigned int id) val &= ~POLHS_HIGH; val &= ~POLVS_HIGH; dpu_dec_write(dec, POLARITYCTRL, val); + + disengcfg_sig_select(dec, DEC_SIG_SEL_FRAMEGEN); } int dpu_dec_init(struct dpu_soc *dpu, unsigned int id, diff --git a/include/video/dpu.h b/include/video/dpu.h index 0155fbebf677..07824f64298e 100644 --- a/include/video/dpu.h +++ b/include/video/dpu.h @@ -110,6 +110,13 @@ typedef enum { } dpu_block_id_t; typedef enum { + DEC_SIG_SEL_FRAMEGEN = 0, + DEC_SIG_SEL_GAMMACOR, + DEC_SIG_SEL_MATRIX, + DEC_SIG_SEL_DITHER, +} dec_sig_sel_t; + +typedef enum { ED_SRC_DISABLE = ID_NONE, ED_SRC_BLITBLEND9 = ID_BLITBLEND9, ED_SRC_CONSTFRAME0 = ID_CONSTFRAME0, @@ -409,6 +416,7 @@ struct dpu_constframe *dpu_aux_cf_peek(struct dpu_constframe *cf); /* Display Engine Configuration Unit */ struct dpu_disengcfg; +void disengcfg_sig_select(struct dpu_disengcfg *dec, dec_sig_sel_t sig_sel); struct dpu_disengcfg *dpu_dec_get(struct dpu_soc *dpu, int id); void dpu_dec_put(struct dpu_disengcfg *dec); struct dpu_disengcfg *dpu_aux_dec_peek(struct dpu_disengcfg *dec); |