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| author | Steve Cornelius <steve.cornelius@freescale.com> | 2012-08-01 16:09:27 -0700 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2012-08-06 14:07:08 +0800 |
| commit | 65069a963114d88cea3f6b200148b2215369c76a (patch) | |
| tree | ba1e30447e031ae671b29ce8fd107823f82062ba /Documentation/arm/Interrupts | |
| parent | 596f96c040ba21b9d5e207adb032b68a04029218 (diff) | |
ENGR00219164: caam: limit AXI pipeline depth = 1 on mx6 for errata
This patch limits AXI pipeline depth to 1 as a workaround for errta
TKT134813, the write
concurrency problem on mx6.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'Documentation/arm/Interrupts')
0 files changed, 0 insertions, 0 deletions