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authorAnders Berg <anders.berg@lsi.com>2014-05-23 11:08:35 +0200
committerArnd Bergmann <arnd@arndb.de>2014-05-23 18:18:39 +0200
commit1d22924e1c4e299337e86e290c02c3e3eb43b608 (patch)
tree53ebde5a7a8bef8e3ac50be57733505110b287ba /Documentation/devicetree/bindings/arm/axxia.txt
parenta798c10faf62a505d24e5f6213fbaf904a39623f (diff)
ARM: Add platform support for LSI AXM55xx SoC
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15 cores (in a 4x4 cluster configuration). The cores within each cluster share an L2 cache, and the clusters are connected to each other via a CCN-504 cache coherent interconnect. This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located above 4GB in the memory map. Signed-off-by: Anders Berg <anders.berg@lsi.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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+Axxia AXM55xx device tree bindings
+
+Boards using the AXM55xx SoC need to have the following properties:
+
+Required root node property:
+
+ - compatible = "lsi,axm5516"
+
+Boards:
+
+ LSI AXM5516 Validation board (Amarillo)
+ compatible = "lsi,axm5516-amarillo", "lsi,axm5516"