summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/arm/mediatek
diff options
context:
space:
mode:
authorSean Wang <sean.wang@mediatek.com>2018-04-27 16:14:43 +0800
committerStephen Boyd <sboyd@kernel.org>2018-05-15 15:21:37 -0700
commit47b65a4a74e5ed9350a8fa11680ce08c2eb4f480 (patch)
tree3932af771fe0021adeef9b4e8d6ebe6f1e154605 /Documentation/devicetree/bindings/arm/mediatek
parent60cc43fc888428bb2f18f08997432d426a243338 (diff)
dt-bindings: clock: mediatek: add g3dsys bindings
Add bindings to g3dsys providing necessary clock and reset control to Mali-450. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/mediatek')
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt30
1 files changed, 30 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
new file mode 100644
index 000000000000..7de43bf41fdc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
@@ -0,0 +1,30 @@
+MediaTek g3dsys controller
+============================
+
+The MediaTek g3dsys controller provides various clocks and reset controller to
+the GPU.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt2701-g3dsys", "syscon":
+ for MT2701 SoC
+ - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
+ for MT7623 SoC
+- #clock-cells: Must be 1
+- #reset-cells: Must be 1
+
+The g3dsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+g3dsys: clock-controller@13000000 {
+ compatible = "mediatek,mt7623-g3dsys",
+ "mediatek,mt2701-g3dsys",
+ "syscon";
+ reg = <0 0x13000000 0 0x200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};