diff options
| author | Will Deacon <will.deacon@arm.com> | 2015-03-06 11:54:08 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-03-24 15:09:47 +0000 |
| commit | 71bbf038eaa44a80dd6df0da7c708d4618172fe0 (patch) | |
| tree | 254618379bbb6b6efc4de039eee350e0ec2a86f9 /Documentation/devicetree/bindings/arm/pmu.txt | |
| parent | 91d57155dc5ab4b311624b7ee570339b6af19ad5 (diff) | |
dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity
The current ARM PMU binding relies on the PMU interrupts being listed in
CPU logical order, which the device-tree author simply cannot know
anything about.
This patch introduces a new "interrupt-affinity" property, which makes
the relationship between the PMU interrupts and their corresponding
CPU explicit.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/pmu.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/pmu.txt | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt index 75ef91d08f3b..f52d05660dc9 100644 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ b/Documentation/devicetree/bindings/arm/pmu.txt @@ -24,6 +24,13 @@ Required properties: Optional properties: +- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles + to CPU nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + This property should be present when there is more than + a single SPI. + - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd events. |