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authorRoger Quadros <rogerq@ti.com>2015-07-30 14:49:23 +0300
committerRoger Quadros <rogerq@ti.com>2016-04-15 11:52:28 +0300
commit384258f252727c67772bbd48dad3185a30ba50d3 (patch)
treedd753eb5c2977384b4885878394f4bc0946d95f1 /Documentation/devicetree/bindings/bus
parent512d73d1c64f15da9cdcdcdfba3cd8db0d4d94cc (diff)
memory: omap-gpmc: Implement IRQ domain for NAND IRQs
GPMC provides 2 interrupts for NAND use. i.e. fifoevent and termcount. Use IRQ domain for this. NAND device tree node can then get the necessary interrupts by using gpmc as the interrupt parent. Legacy boot uses gpmc_get_client_irq to get the NAND interrupts from the GPMC IRQ domain. Get rid of custom bitmasks and use IRQ domain for that as well. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'Documentation/devicetree/bindings/bus')
-rw-r--r--Documentation/devicetree/bindings/bus/ti-gpmc.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 01683707060b..13f13786f992 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -32,6 +32,12 @@ Required properties:
bootloader) are used for the physical address decoding.
As this will change in the future, filling correct
values here is a requirement.
+ - interrupt-controller: The GPMC driver implements and interrupt controller for
+ the NAND events "fifoevent" and "termcount".
+ The interrupt number mapping is as follows
+ 0 - NAND_fifoevent
+ 1 - NAND_termcount
+ - interrupt-cells: Must be set to 2
Timing properties for child nodes. All are optional and default to 0.
@@ -130,6 +136,8 @@ Example for an AM33xx board:
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
+ interrupt-controller;
+ #interrupt-cells = <2>;
/* child nodes go here */
};