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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2013-07-02 09:01:31 -0700
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2013-07-02 09:01:31 -0700
commit27eb2c4b3d3e13f376a359e293c212a2e9407af5 (patch)
tree556aa7b5cd6eeb4214dec129c789515157187010 /Documentation/devicetree/bindings/clock/altr_socfpga.txt
parent5705b8aca5a80141de5637ff0e23b31b26f2c5bf (diff)
parent67bf12ca50d524f9e225347fe63533562e2004de (diff)
Merge branch 'next' into for-linus
Prepare first set of updates for 3.11 merge window.
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+Device Tree Clock bindings for Altera's SoCFPGA platform
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+ "altr,socfpga-pll-clock" - for a PLL clock
+ "altr,socfpga-perip-clock" - The peripheral clock divided from the
+ PLL clock.
+- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
+- clocks : shall be the input parent clock phandle for the clock. This is
+ either an oscillator or a pll output.
+- #clock-cells : from common clock binding, shall be set to 0.
+
+Optional properties:
+- fixed-divider : If clocks have a fixed divider value, use this property.