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author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2013-07-02 09:01:31 -0700 |
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committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2013-07-02 09:01:31 -0700 |
commit | 27eb2c4b3d3e13f376a359e293c212a2e9407af5 (patch) | |
tree | 556aa7b5cd6eeb4214dec129c789515157187010 /Documentation/devicetree/bindings/clock/altr_socfpga.txt | |
parent | 5705b8aca5a80141de5637ff0e23b31b26f2c5bf (diff) | |
parent | 67bf12ca50d524f9e225347fe63533562e2004de (diff) |
Merge branch 'next' into for-linus
Prepare first set of updates for 3.11 merge window.
Diffstat (limited to 'Documentation/devicetree/bindings/clock/altr_socfpga.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/altr_socfpga.txt | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt new file mode 100644 index 000000000000..bd0c8416a5c8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -0,0 +1,18 @@ +Device Tree Clock bindings for Altera's SoCFPGA platform + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "altr,socfpga-pll-clock" - for a PLL clock + "altr,socfpga-perip-clock" - The peripheral clock divided from the + PLL clock. +- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. +- clocks : shall be the input parent clock phandle for the clock. This is + either an oscillator or a pll output. +- #clock-cells : from common clock binding, shall be set to 0. + +Optional properties: +- fixed-divider : If clocks have a fixed divider value, use this property. |