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authorMarek Szyprowski <m.szyprowski@samsung.com>2016-11-17 12:42:52 +0100
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-11-17 13:58:37 +0100
commit9a81188e4c8abbaab92d5b77850dd855f5487440 (patch)
treeaa496748a0053c572304341000b1e317bdfaf3d1 /Documentation/devicetree/bindings/clock/exynos5433-clock.txt
parent1001354ca34179f3db924eb66672442a173147dc (diff)
clk: exynos5433: Fix parent clocks for FSYS block
The proper parent clock for FSYS block is "aclk_fsys_200" according to the Exynos5433 reference manual. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/exynos5433-clock.txt')
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5433-clock.txt6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 63379b04e052..ffff67a0e9cd 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -79,7 +79,7 @@ Required Properties:
Input clocks for fsys clock controller:
- oscclk
- sclk_ufs_mphy
- - div_aclk_fsys_200
+ - aclk_fsys_200
- sclk_pcie_100_fsys
- sclk_ufsunipro_fsys
- sclk_mmc2_fsys
@@ -235,7 +235,7 @@ Example 2: Examples of clock controller nodes are listed below.
clock-names = "oscclk",
"sclk_ufs_mphy",
- "div_aclk_fsys_200",
+ "aclk_fsys_200",
"sclk_pcie_100_fsys",
"sclk_ufsunipro_fsys",
"sclk_mmc2_fsys",
@@ -245,7 +245,7 @@ Example 2: Examples of clock controller nodes are listed below.
"sclk_usbdrd30_fsys";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_UFS_MPHY>,
- <&cmu_top CLK_DIV_ACLK_FSYS_200>,
+ <&cmu_top CLK_ACLK_FSYS_200>,
<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
<&cmu_top CLK_SCLK_MMC2_FSYS>,