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| author | Emilio López <emilio@elopez.com.ar> | 2013-12-23 00:32:37 -0300 |
|---|---|---|
| committer | Emilio López <emilio@elopez.com.ar> | 2013-12-28 17:08:17 -0300 |
| commit | d584c1331d6421e2387eab10b11fa6f08b4a4b5f (patch) | |
| tree | 7c1d6a78ae45ac0aed61a96ae856f9cd295f70a3 /Documentation/devicetree/bindings/clock/sunxi.txt | |
| parent | 5f4e0be3a72325fbc4d349a847cc9b2edd85b6d2 (diff) | |
clk: sunxi: add PLL5 and PLL6 support
This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/sunxi.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/sunxi.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index b8c6cc449a3e..80b2a39b17a2 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -9,6 +9,8 @@ Required properties: "allwinner,sun4i-osc-clk" - for a gatable oscillator "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 + "allwinner,sun4i-pll5-clk" - for the PLL5 clock + "allwinner,sun4i-pll6-clk" - for the PLL6 clock "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock "allwinner,sun4i-axi-clk" - for the AXI clock "allwinner,sun4i-axi-gates-clk" - for the AXI gates |