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authorIvan Khoronzhuk <ivan.khoronzhuk@ti.com>2014-05-23 16:32:39 -0400
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2014-05-27 09:46:39 -0400
commitd30982b93a79aafa688e7df1f6948ad28bb94e89 (patch)
treef68de375a50253492b06181cbd27f6bec600d65e /Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
parentcaee0055337ab96a5af844fba6e72d518d7287dd (diff)
Documentation: dt: add bindings for keystone pll control controller
The main pll controller used to drive theC66x CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and the NETCP modules) requires a PLL Controller to manage the various clock divisions, gating, and synchronization. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [santosh.shilimkar@ti.com: Fixed the subject line] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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+* Device tree bindings for Texas Instruments keystone pll controller
+
+The main pll controller used to drive theC66x CorePacs, the switch fabric,
+and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
+the NETCP modules) requires a PLL Controller to manage the various clock
+divisions, gating, and synchronization.
+
+Required properties:
+
+- compatible: "ti,keystone-pllctrl", "syscon"
+
+- reg: contains offset/length value for pll controller
+ registers space.
+
+Example:
+
+pllctrl: pll-controller@0x02310000 {
+ compatible = "ti,keystone-pllctrl", "syscon";
+ reg = <0x02310000 0x200>;
+};