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| author | Michael Turquette <mturquette@baylibre.com> | 2016-06-06 18:08:15 -0700 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2016-06-22 18:05:47 -0700 |
| commit | 4a47295144ddbcf802fcddb3d7c0736d9a1f2e40 (patch) | |
| tree | e988e9fddbcae63d64496b086d9be5c81e2bbc21 /Documentation/devicetree/bindings/clock | |
| parent | 1c50da4f27cbfb588b59684b55eb7a087bb26ed1 (diff) | |
clk: meson: fractional pll support
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
0 files changed, 0 insertions, 0 deletions